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fix(ida): replace __getattribute__ with __getattr__ #1231

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Merged
xwings merged 1 commit into from
Sep 24, 2022
Merged

fix(ida): replace __getattribute__ with __getattr__ #1231

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6 changes: 3 additions & 3 deletions qiling/extensions/idaplugin/qilingida.py
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Original file line number Diff line number Diff line change
Expand Up @@ -1466,7 +1466,7 @@ def _force_execution_by_parsing_assembly(self, ql, ida_addr):
if "x86" in IDA.get_ql_arch_string(): # cmovlg eax, ebx
reg1 = IDA.print_operand(ida_addr, 0).lower()
reg2 = IDA.print_operand(ida_addr, 1).lower()
reg2_val = ql.arch.regs.__getattribute__(reg2)
reg2_val = ql.arch.regs.__getattr__(reg2)
logging.info(f"Force set {reg1} to {hex(reg2_val)}")
ql.arch.regs.__setattr__(reg1, reg2_val)
return True
Expand All @@ -1486,7 +1486,7 @@ def _force_execution_by_parsing_assembly(self, ql, ida_addr):
elif "csel" in instr: # csel dst, src1, src2, cond
dst = IDA.print_operand(ida_addr, 0).lower()
src = IDA.print_operand(ida_addr, 2).lower()
src_val = ql.arch.regs.__getattribute__(src)
src_val = ql.arch.regs.__getattr__(src)
logging.info(f"Force set {dst} to {hex(src_val)}")
ql.arch.regs.__setattr__(dst, src_val)
return True
Expand Down Expand Up @@ -1597,7 +1597,7 @@ def _log_verbose(self, ql, addr, size):
registers = [ k for k in ql.arch.regs.register_mapping.keys() if type(k) is str ]
for idx in range(0, len(registers), 3):
regs = registers[idx:idx+3]
s = "\t".join(map(lambda v: f"{v:4}: {ql.arch.regs.__getattribute__(v):016x}", regs))
s = "\t".join(map(lambda v: f"{v:4}: {ql.arch.regs.__getattr__(v):016x}", regs))
logging.debug(s)

# Q: Why we need emulation to help us find real control flow considering there are some
Expand Down