June 2019 Improvements #10
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FPGA DVI LUT/ff usage on Vivado 2019.1 with this change is only 103/72. DVI Pmod and VGA LUT usage increases slightly on 2019.1.
Additional utilization information.
I was unable to resolve the warning when using the xpm_cdc_async_rst macro. My design has the same warning, but has the advantage of being standard Verilog. Thanks to markg@prosensing.com for help with reset warnings and design.
Includes gradient test that exercises more functionality. Better utilization calculations.
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Better OSERDES2 async reset. Thanks to markg@prosensing.com for help with this.
Improved test cards: including gradient test that exercises more functionality.
Better utilization calculations.