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WillGreenWillGreen
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Merge pull request #10 from projf/oserdes-async-reset
June 2019 Improvements
2 parents ce09da4 + 06581d8 commit 0e310d2

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9 files changed

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‎README.md‎

Lines changed: 14 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -115,15 +115,20 @@ You can also see the full output from the [Python model](model/tmds-test-python.
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116116

117117
## Resource Utilization
118-
The display controller is lightweight, fitting into even the smallest FPGA:
118+
The display controller is lightweight, fitting comfortably into even small FPGAs.
119119

120-
Artix-7
121-
Demo LUT FF
122-
---------------------------
123-
DVI on FPGA 125 76
124-
DVI BML 3-bit 67 32
125-
DVI BML 24-bit TBC TBC
126-
VGA 67 32
120+
The following table shows utilization of the display-controller with the gradient test card at a resolution of 640x480.
127121

128-
For reference an Artix A35T has 20,800 LUT6 and 41,600 FF, so even full TMDS uses well under 1% of the LUTs. Values are for demos using the simple test card module. Synthesized using Vivado 2018.3 with default options.
122+
Artix-7
123+
Interface LUT FF
124+
-----------------------------
125+
DVI on FPGA 278 78
126+
DVI BML 3-bit 49 32
127+
DVI BML 24-bit TBC TBC
128+
VGA 12-bit 67 32
129+
-----------------------------
130+
Synthesized and implemented with Vivado 2019.1 using default options.
129131

132+
For comparison an Artix A35T has 20,800 LUT6 and 41,600 FF, while the tiny Spartan 7S6 has 3,752 LUT6 and 7,500 FF.
133+
134+
NB. If you drive the "DVI on FPGA" display controller with a few fixed colours, such as the simple test bench, the optimizer removes a significant part of the design, resulting in misleadingly low utilization.

‎hdl/demo/display_demo_dvi.v‎

Lines changed: 36 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -10,8 +10,8 @@
1010
// * display_timings
1111
// * dvi_generator
1212
// * serializer_10to1
13-
// * test_card
1413
// * tmds_encoder_dvi
14+
// * test_card_simple or another test card
1515

1616
module display_demo_dvi(
1717
input wire CLK, // board clock: 100 MHz on Arty/Basys3/Nexys
@@ -83,20 +83,44 @@ module display_demo_dvi(
8383
.o_y(y)
8484
);
8585

86-
// Test Card Generation
87-
wire red, green, blue;
88-
test_card #(
89-
.H_RES(1280),
90-
.V_RES(720)
91-
)
92-
test_card_inst (
86+
// test card colour output
87+
wire [7:0] red;
88+
wire [7:0] green;
89+
wire [7:0] blue;
90+
91+
// Test Card: Simple - ENABLE ONE TEST CARD INSTANCE ONLY
92+
test_card_simple #(
93+
.H_RES(1280) // horizontal resolution
94+
) test_card_inst (
9395
.i_x(x),
94-
.i_y(y),
9596
.o_red(red),
9697
.o_green(green),
9798
.o_blue(blue)
9899
);
99100

101+
// // Test Card: Squares - ENABLE ONE TEST CARD INSTANCE ONLY
102+
// test_card_squares #(
103+
// .H_RES(1280), // horizontal resolution
104+
// .V_RES(720) // vertical resolution
105+
// )
106+
// test_card_inst (
107+
// .i_x(x),
108+
// .i_y(y),
109+
// .o_red(red),
110+
// .o_green(green),
111+
// .o_blue(blue)
112+
// );
113+
114+
// // Test Card: Gradient - ENABLE ONE TEST CARD INSTANCE ONLY
115+
// localparam GRAD_STEP = 2; // step right shift: 480=2, 720=2, 1080=3
116+
// test_card_gradient test_card_inst (
117+
// .i_y(y[GRAD_STEP+7:GRAD_STEP]),
118+
// .i_x(x[5:0]),
119+
// .o_red(red),
120+
// .o_green(green),
121+
// .o_blue(blue)
122+
// );
123+
100124
// TMDS Encoding and Serialization
101125
wire tmds_ch0_serial, tmds_ch1_serial, tmds_ch2_serial, tmds_chc_serial;
102126
dvi_generator dvi_out (
@@ -105,9 +129,9 @@ module display_demo_dvi(
105129
.i_clk_lock(clk_lock),
106130
.i_rst(rst),
107131
.i_de(de),
108-
.i_data_ch0({8{blue}}),
109-
.i_data_ch1({8{green}}),
110-
.i_data_ch2({8{red}}),
132+
.i_data_ch0(blue),
133+
.i_data_ch1(green),
134+
.i_data_ch2(red),
111135
.i_ctrl_ch0({v_sync, h_sync}),
112136
.i_ctrl_ch1(2'b00),
113137
.i_ctrl_ch2(2'b00),

‎hdl/demo/display_demo_dvi_pmod3.v‎

Lines changed: 37 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88
// This demo requires the following Verilog modules:
99
// * display_clocks
1010
// * display_timings
11-
// * test_card
11+
// * test_card_simple or another test card
1212

1313
module display_demo_dvi_pmod3(
1414
input wire CLK, // board clock: 100 MHz on Arty/Basys3/Nexys
@@ -78,26 +78,51 @@ module display_demo_dvi_pmod3(
7878
.o_y(y)
7979
);
8080

81-
// Test Card Generation
82-
wire red, green, blue;
83-
test_card #(
84-
.H_RES(640),
85-
.V_RES(480)
86-
)
87-
test_card_inst (
81+
// test card colour output
82+
wire [7:0] red;
83+
wire [7:0] green;
84+
wire [7:0] blue;
85+
86+
// Test Card: Simple - ENABLE ONE TEST CARD INSTANCE ONLY
87+
test_card_simple #(
88+
.H_RES(640) // horizontal resolution
89+
) test_card_inst (
8890
.i_x(x),
89-
.i_y(y),
9091
.o_red(red),
9192
.o_green(green),
9293
.o_blue(blue)
9394
);
9495

96+
// // Test Card: Squares - ENABLE ONE TEST CARD INSTANCE ONLY
97+
// test_card_squares #(
98+
// .H_RES(640), // horizontal resolution
99+
// .V_RES(480) // vertical resolution
100+
// )
101+
// test_card_inst (
102+
// .i_x(x),
103+
// .i_y(y),
104+
// .o_red(red),
105+
// .o_green(green),
106+
// .o_blue(blue)
107+
// );
108+
109+
// // Test Card: Gradient - ENABLE ONE TEST CARD INSTANCE ONLY
110+
// localparam GRAD_STEP = 2; // step right shift: 480=2, 720=2, 1080=3
111+
// test_card_gradient test_card_inst (
112+
// .i_x(x[5:0]),
113+
// .i_y(y[GRAD_STEP+7:GRAD_STEP]),
114+
// .o_red(red),
115+
// .o_green(green),
116+
// .o_blue(blue)
117+
// );
118+
95119
// 3-bit DVI Output
120+
// Only 1 bit per colours, so we take the MSB of each colour
96121
assign DVI_HS = h_sync;
97122
assign DVI_VS = v_sync;
98123
assign DVI_CLK = pix_clk;
99124
assign DVI_DE = de;
100-
assign DVI_R = de & red;
101-
assign DVI_G = de & green;
102-
assign DVI_B = de & blue;
125+
assign DVI_R = de ? red[7] : 1'b0;
126+
assign DVI_G = de ? green[7] : 1'b0;
127+
assign DVI_B = de ? blue[7] : 1'b0;
103128
endmodule

‎hdl/demo/display_demo_vga.v‎

Lines changed: 37 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88
// This demo requires the following Verilog modules:
99
// * display_clocks
1010
// * display_timings
11-
// * test_card
11+
// * test_card_simple or another test card
1212

1313
module display_demo_vga(
1414
input wire CLK, // board clock: 100 MHz on Arty/Basys3/Nexys
@@ -76,24 +76,49 @@ module display_demo_vga(
7676
.o_y(y)
7777
);
7878

79-
// Test Card Generation
80-
wire red, green, blue;
81-
test_card #(
82-
.H_RES(640),
83-
.V_RES(480)
84-
)
85-
test_card_inst (
79+
// test card colour output
80+
wire [7:0] red;
81+
wire [7:0] green;
82+
wire [7:0] blue;
83+
84+
// Test Card: Simple - ENABLE ONE TEST CARD INSTANCE ONLY
85+
test_card_simple #(
86+
.H_RES(640) // horizontal resolution
87+
) test_card_inst (
8688
.i_x(x),
87-
.i_y(y),
8889
.o_red(red),
8990
.o_green(green),
9091
.o_blue(blue)
9192
);
9293

94+
// // Test Card: Squares - ENABLE ONE TEST CARD INSTANCE ONLY
95+
// test_card_squares #(
96+
// .H_RES(640), // horizontal resolution
97+
// .V_RES(480) // vertical resolution
98+
// )
99+
// test_card_inst (
100+
// .i_x(x),
101+
// .i_y(y),
102+
// .o_red(red),
103+
// .o_green(green),
104+
// .o_blue(blue)
105+
// );
106+
107+
// // Test Card: Gradient - ENABLE ONE TEST CARD INSTANCE ONLY
108+
// localparam GRAD_STEP = 2; // step right shift: 480=2, 720=2, 1080=3
109+
// test_card_gradient test_card_inst (
110+
// .i_x(x[5:0]),
111+
// .i_y(y[GRAD_STEP+7:GRAD_STEP]),
112+
// .o_red(red),
113+
// .o_green(green),
114+
// .o_blue(blue)
115+
// );
116+
93117
// VGA Output
118+
// VGA Pmod is 12-bit so we take the upper nibble of each colour
94119
assign VGA_HS = h_sync;
95120
assign VGA_VS = v_sync;
96-
assign VGA_R = {4{de & red}};
97-
assign VGA_G = {4{de & green}};
98-
assign VGA_B = {4{de & blue}};
121+
assign VGA_R = de ? red[7:4] : 4'b0;
122+
assign VGA_G = de ? green[7:4] : 4'b0;
123+
assign VGA_B = de ? blue[7:4] : 4'b0;
99124
endmodule

‎hdl/demo/test_card_gradient.v‎

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,23 @@
1+
`timescale 1ns / 1ps
2+
`default_nettype none
3+
4+
// Project F: Display Controller Test Card: Gradient
5+
// (C)2019 Will Green, Open Source Hardware released under the MIT License
6+
// Learn more at https://projectf.io
7+
8+
module test_card_gradient (
9+
input wire [5:0] i_x,
10+
input wire [7:0] i_y,
11+
output wire [7:0] o_red,
12+
output wire [7:0] o_green,
13+
output wire [7:0] o_blue
14+
);
15+
16+
localparam base_red = 8'h00;
17+
localparam base_green = 8'h10;
18+
localparam base_blue = 8'h4C;
19+
20+
assign o_red = base_red + i_y + i_x;
21+
assign o_green = base_green + i_y;
22+
assign o_blue = base_blue + i_y;
23+
endmodule

‎hdl/demo/test_card_simple.v‎

Lines changed: 17 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -5,30 +5,27 @@
55
// (C)2019 Will Green, Open Source Hardware released under the MIT License
66
// Learn more at https://projectf.io
77

8-
module test_card_simple #(
9-
H_RES=640,
10-
V_RES=480
11-
)
12-
(
8+
module test_card_simple #(H_RES=640) (
139
input wire [15:0] i_x,
14-
input wire [15:0] i_y,
15-
output wire o_red,
16-
output wire o_green,
17-
output wire o_blue
10+
output wire [7:0] o_red,
11+
output wire [7:0] o_green,
12+
output wire [7:0] o_blue
1813
);
1914

20-
localparam HR = H_RES; // horizontal resolution (pixels)
21-
localparam VR = V_RES; // vertical resolution (lines)
22-
localparam BW = 16; // border width
15+
localparam HW = H_RES >> 3; // horizontal colour width = H_RES / 8
2316

24-
// Borders
25-
wire top = (i_x >= 0) & (i_y >= 0) & (i_x < HR) & (i_y < BW);
26-
wire btm = (i_x >= 0) & (i_y >= VR-BW) & (i_x < HR) & (i_y < VR);
27-
wire lft = (i_x >= 0) & (i_y >= 0) & (i_x < BW) & (i_y < VR);
28-
wire rgt = (i_x >= HR-BW) & (i_y >= 0) & (i_x < HR) & (i_y < VR);
17+
// Bands
18+
wire b0 = (i_x >= 0 ) & (i_x < HW );
19+
wire b1 = (i_x >= HW ) & (i_x < HW * 2);
20+
wire b2 = (i_x >= HW * 2) & (i_x < HW * 3);
21+
wire b3 = (i_x >= HW * 3) & (i_x < HW * 4);
22+
wire b4 = (i_x >= HW * 4) & (i_x < HW * 5);
23+
wire b5 = (i_x >= HW * 5) & (i_x < HW * 6);
24+
wire b6 = (i_x >= HW * 6) & (i_x < HW * 7);
25+
wire b7 = (i_x >= HW * 7) & (i_x < HW * 8);
2926

3027
// Colour Output
31-
assign o_red = lft | top;
32-
assign o_green = btm | top;
33-
assign o_blue = rgt | top;
28+
assign o_red = {8{b0 | b1 | b5}} + {1'b0,{7{b6}}} + {2'b0,{6{b7}}};
29+
assign o_green = {8{b1 | b2 | b3}} + {1'b0,{7{b6}}} + {2'b0,{6{b7}}};
30+
assign o_blue = {8{b3 | b4 | b5}} + {1'b0,{7{b6}}} + {2'b0,{6{b7}}};
3431
endmodule

hdl/demo/test_card.v renamed to hdl/demo/test_card_squares.v

Lines changed: 9 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,20 +1,19 @@
11
`timescale 1ns / 1ps
22
`default_nettype none
33

4-
// Project F: Display Controller Test Card
4+
// Project F: Display Controller Test Card: Squares
55
// (C)2019 Will Green, Open Source Hardware released under the MIT License
66
// Learn more at https://projectf.io
77

8-
module test_card #(
8+
module test_card_squares #(
99
H_RES=640,
1010
V_RES=480
11-
)
12-
(
11+
) (
1312
input wire [15:0] i_x,
1413
input wire [15:0] i_y,
15-
output wire o_red,
16-
output wire o_green,
17-
output wire o_blue
14+
output wire [7:0] o_red,
15+
output wire [7:0] o_green,
16+
output wire [7:0] o_blue
1817
);
1918

2019
localparam HR = H_RES; // horizontal resolution (pixels)
@@ -49,7 +48,7 @@ module test_card #(
4948
wire lns_8 = (i_y >= SY) & (i_y <= SY + 2*SQ) & ((i_x == SX + 8*SQ + 3*LS) | (i_x == SX + 10*SQ - 3*LS));
5049

5150
// Colour Output
52-
assign o_red = lft | top | lns_1 | lns_4 | lns_5 | lns_8 | sq_b | sq_e;
53-
assign o_green = btm | top | lns_2 | lns_4 | lns_6 | lns_8 | sq_a | sq_d | sq_e;
54-
assign o_blue = rgt | top | lns_3 | lns_4 | lns_7 | lns_8 | sq_c | sq_e;
51+
assign o_red = {8{ lft | top | lns_1 | lns_4 | lns_5 | lns_8 | sq_b | sq_e }};
52+
assign o_green = {8{ btm | top | lns_2 | lns_4 | lns_6 | lns_8 | sq_a | sq_d | sq_e }};
53+
assign o_blue = {8{ rgt | top | lns_3 | lns_4 | lns_7 | lns_8 | sq_c | sq_e }};
5554
endmodule

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