Merge pull request #9 from projf/no-async-timings

No async display timings

Author: WillGreen

README.md

@@ -1,4 +1,4 @@
-# Project F Display Controller 
+# Project F Display Controller
 
 The Project F display controller makes it easy to add video output to FPGA projects. It's written in Verilog and supports VGA, DVI, and HDMI displays. It includes full configuration for 640x480, 800x600, 1280x720, and 1920x1080, as well as the ability to define custom resolutions. This design and its documentation are licensed under the MIT License.
 
@@ -22,12 +22,12 @@ This design supports displays using VGA, DVI, and HDMI.
 
 **VGA** support is straightforward; you can see an example in the [VGA demo](hdl/demo/display_demo_vga.v). If you're building your own hardware, then [Retro Ramblings](http://retroramblings.net/?p=190) has a good example of creating a register ladder DAC. If you're looking for a ready-made VGA output, then the [VGA Pmod](https://reference.digilentinc.com/reference/pmod/pmodvga/start) is a good option for around $10.
 
-**DVI** & **HDMI** use [transition-minimized differential signalling](https://en.wikipedia.org/wiki/Transition-minimized_differential_signaling) (TMDS) to transmit video over high-speed serial links. HDMI provides extra functionality over DVI, including audio support, but all HDMI displays should accept a standard DVI signal without issue. 
+**DVI** & **HDMI** use [transition-minimized differential signalling](https://en.wikipedia.org/wiki/Transition-minimized_differential_signaling) (TMDS) to transmit video over high-speed serial links. HDMI provides extra functionality over DVI, including audio support, but all HDMI displays should accept a standard DVI signal without issue.
 
-The display controller offers two types of TMDS generation: 
+The display controller offers two types of TMDS generation:
 
 * Direct generation on FPGA
-* [Black Mesa Labs DVI Pmod](https://blackmesalabs.wordpress.com/2017/12/15/bml-hdmi-video-for-fpgas-over-pmod/)  
+* [Black Mesa Labs DVI Pmod](https://blackmesalabs.wordpress.com/2017/12/15/bml-hdmi-video-for-fpgas-over-pmod/)
 
 Direct TMDS generation on FPGA requires high-frequency clocks (742.5 MHz for 720p60) and SerDes but allows full control of the signal including HDMI features. HDMI support is currently via backwards compatibility with DVI: any standard HDMI display should accept DVI signals. However, this display controller lacks support for audio or advanced HDMI features at present.
 
@@ -36,14 +36,14 @@ The Black Mesa Labs (BML) Pmod is based on the Texas Instruments [TFP410](http:/
 
 ## Display Resolution Support
 The following four display resolutions are tested and included by default (all at 60 Hz refresh rate):
-    
-     Resolution  Ratio   Clock     
+
+     Resolution  Ratio   Clock
      640 x  480    4:3   25.20 MHz [1]
      800 x  600    4:3   40.00 MHz
-    1280 x  720   16:9   74.25 MHz     
-    1920 x 1080   16:9  148.50 MHz [2]  
+    1280 x  720   16:9   74.25 MHz
+    1920 x 1080   16:9  148.50 MHz [2]
 
-You can easily add timings for other resolutions; see [demos](#demos) for how to do this. 
+You can easily add timings for other resolutions; see [demos](#demos) for how to do this.
 
 _[1] The canonical clock for 640x480 60Hz is 25.175 MHz, but 25.2 MHz is within VESA spec and easier to generate._
 
@@ -91,9 +91,9 @@ We haven't formally verified the design yet, but plan to do this for the display
 
 
 ## TMDS Encoder Model
-The display controller includes a simple [Python model](model/tmds.py) to help with TMDS encoder development. 
+The display controller includes a simple [Python model](model/tmds.py) to help with TMDS encoder development.
 
-There are two steps to TMDS encoding: applying XOR or XNOR to the bits to minimize transitions and keeping the overall number of 1s and 0s similar to ensure DC balance. The first step depends only on the current input value, so it is easy to test. However, balancing depends on the previous values, which makes testing harder; this is where the model is particularly useful. 
+There are two steps to TMDS encoding: applying XOR or XNOR to the bits to minimize transitions and keeping the overall number of 1s and 0s similar to ensure DC balance. The first step depends only on the current input value, so it is easy to test. However, balancing depends on the previous values, which makes testing harder; this is where the model is particularly useful.
 
 By default, the Python model encodes all 256 possible 8-bit values in order, but it's easy to change the script to handle other combinations. `A0, A1, B0, or B1` show which of the four balancing options was taken: you can see what they do in the [Python source](model/tmds.py) or [Verilog design](hdl/tmds_encoder_dvi.v).
 
@@ -115,7 +115,7 @@ You can also see the full output from the [Python model](model/tmds-test-python.
 
 
 ## Resource Utilization
-The display controller is lightweight, fitting into even the smallest FPGA: 
+The display controller is lightweight, fitting into even the smallest FPGA:
 
                       Artix-7
     Demo             LUT     FF

doc/modules.md

@@ -10,7 +10,7 @@ See [README](/README.md) for more documentation.
 ## Contents
 
 - **[Architecture](#architecture)**
-- **[Display Clocks](#display-clocks)** ([hdl](/hdl/display_clocks.v)) - pixel and high-speed clocks for TMDS 
+- **[Display Clocks](#display-clocks)** ([hdl](/hdl/display_clocks.v)) - pixel and high-speed clocks for TMDS
 - **[Display Timings](#display-timings)** ([hdl](/hdl/display_timings.v)) - generates display timings, including horizontal and vertical sync
 - **[DVI Generator](#dvi-generator)** ([hdl](/hdl/dvi_generator.v)) - uses `serializer_10to1` and `tmds_encode_dvi` to generate a DVI signal
 
@@ -84,7 +84,7 @@ The display timings generator turns timing parameters into appropriately timed s
 * `i_pixclk` - pixel clock
 * `i_rst` - reset (active high)
 
-The pixel clock must be suitable for the timings given in the parameters (see display clocks, above). 
+The pixel clock must be suitable for the timings given in the parameters (see display clocks, above).
 
 ### Outputs
 
@@ -97,7 +97,7 @@ The pixel clock must be suitable for the timings given in the parameters (see di
 * `o_x [15:0]` - horizontal screen position (active pixels)
 * `o_y [15:0]` - vertical screen position (active pixels)
 
-The positional outputs `(h,v)` and `(x,y)` allow you to determine the current pixel AKA "beam position". The values provided by `h` & `v `include the blanking interval, while `x` & `y` only include valid on-screen positions. For simple drawing or bitmap display you can use `(x,y)` and safely ignore `(h,v)`. However, if you're doing calculations in real time "racing the beam", then you'll want to perform actions in the blanking interval, which is where (h,v) comes in. 
+The positional outputs `(h,v)` and `(x,y)` allow you to determine the current pixel AKA "beam position". The values provided by `h` & `v `include the blanking interval, while `x` & `y` only include valid on-screen positions. For simple drawing or bitmap display you can use `(x,y)` and safely ignore `(h,v)`. However, if you're doing calculations in real time "racing the beam", then you'll want to perform actions in the blanking interval, which is where (h,v) comes in.
 
 Project F considers blanking intervals to occur _before_ active pixels. At the start of a frame (indicated by the `o_frame` signal), you have the blanking intervals in which to work before active pixel drawing occurs. The following sketch this for 1280x720p60 (other resolutions work in the same way):
 
@@ -109,8 +109,8 @@ Horizontal and vertical sync may be active high or low depending on the display
 
 ### Parameters
 
-* `H_RES` - active horizontal resolution in pixels 
-* `V_RES` - active vertical resolution in lines 
+* `H_RES` - active horizontal resolution in pixels
+* `V_RES` - active vertical resolution in lines
 * `H_FP` - horizontal front porch length in pixels
 * `H_SYNC` - horizontal sync length in pixels
 * `H_BP` - horizontal back porch length in pixels
@@ -138,7 +138,7 @@ DVI generator instantiates two other modules to do the actual work: one for [TMD
 * `i_data_ch0 [7:0]` - 8-bit blue colour data (TMDS channel 0)
 * `i_data_ch1 [7:0]` - 8-bit green colour data (TMDS channel 1)
 * `i_data_ch2 [7:0]` - 8-bit red colour data (TMDS channel 2)
-* `i_ctrl_ch0 [1:0]` - channel 0 control data; set to `{v_sync, h_sync}` from [display timings](#display-timings) 
+* `i_ctrl_ch0 [1:0]` - channel 0 control data; set to `{v_sync, h_sync}` from [display timings](#display-timings)
 * `i_ctrl_ch1 [1:0]` - channel 1 control data; set to `2'b00`
 * `i_ctrl_ch2 [1:0]` - channel 2 control data; set to `2'b00`
 
@@ -153,7 +153,7 @@ The output is the four TMDS encoded serial channels ready for output as differen
 
 You can use these signals with `OBUFDS`, for example:
 
-    OBUFDS #(.IOSTANDARD("TMDS_33")) 
+    OBUFDS #(.IOSTANDARD("TMDS_33"))
         tmds_buf_ch0 (.I(tmds_ch0_serial), .O(hdmi_tx_p[0]), .OB(hdmi_tx_n[0]));
 
 Where `hdmi_tx_p[0]` and `hdmi_tx_n[0]` are the differential output pins for TMDS channel 0.

doc/porting.md

@@ -1,4 +1,4 @@
-# Porting the Display Controller 
+# Porting the Display Controller
 
 We strive to create generic HDL designs where possible. However, vendor-specific components are critical to certain functionality, such as high-speed clock generation. The display controller uses three Xilinx-specific components: all display options use the `MMCM` for clock generation, while TMDS encoding on the FPGA requires `OSERDESE2` and `OBUFDS`. Expanded hardware support will be available in future, but in the meantime, we offer the following advice:
 

hdl/demo/display_demo_dvi.v

@@ -6,12 +6,12 @@
 // Learn more at https://projectf.io
 
 // This demo requires the following Verilog modules:
-// * display_clocks
-// * display_timings
-// * dvi_generator
-// * serializer_10to1
-// * test_card
-// * tmds_encoder_dvi 
+//  * display_clocks
+//  * display_timings
+//  * dvi_generator
+//  * serializer_10to1
+//  * test_card
+//  * tmds_encoder_dvi
 
 module display_demo_dvi(
     input  wire CLK,                // board clock: 100 MHz on Arty/Basys3/Nexys
@@ -22,13 +22,13 @@ module display_demo_dvi(
     inout  wire hdmi_tx_rsda,       // DDC bidirectional
     output wire hdmi_tx_clk_n,      // HDMI clock differential negative
     output wire hdmi_tx_clk_p,      // HDMI clock differential positive
-    output wire [2:0] hdmi_tx_n,    // Three HDMI channels differential negative       
+    output wire [2:0] hdmi_tx_n,    // Three HDMI channels differential negative
     output wire [2:0] hdmi_tx_p     // Three HDMI channels differential positive
     );
 
     wire rst = ~RST_BTN;            // reset is active low on Arty & Nexys Video
     // wire rst = RST_BTN;          // reset is active high on Basys3 (BTNC)
-    
+
     // Display Clocks
     wire pix_clk;                   // pixel clock
     wire pix_clk_5x;                // 5x clock for 10:1 DDR SerDes
@@ -43,9 +43,9 @@ module display_demo_dvi(
     )
     display_clocks_inst
     (
-       .i_clk(CLK), 
-       .i_rst(rst), 
-       .o_clk_1x(pix_clk), 
+       .i_clk(CLK),
+       .i_rst(rst),
+       .o_clk_1x(pix_clk),
        .o_clk_5x(pix_clk_5x),
        .o_locked(clk_lock)
     );
@@ -69,12 +69,12 @@ module display_demo_dvi(
         .V_BP(20),                  //      33       23       20        36
         .H_POL(1),                  //       0        1        1         1
         .V_POL(1)                   //       0        1        1         1
-    ) 
-    display_timings_inst (  
+    )
+    display_timings_inst (
         .i_pixclk(pix_clk),
         .i_rst(rst),
-        .o_hs(h_sync), 
-        .o_vs(v_sync), 
+        .o_hs(h_sync),
+        .o_vs(v_sync),
         .o_de(de),
         .o_frame(frame),
         .o_h(),
@@ -86,17 +86,17 @@ module display_demo_dvi(
     // Test Card Generation
     wire red, green, blue;
     test_card #(
-        .H_RES(1280), 
+        .H_RES(1280),
         .V_RES(720)
-    ) 
+    )
     test_card_inst (
         .i_x(x),
         .i_y(y),
         .o_red(red),
         .o_green(green),
         .o_blue(blue)
     );
-    
+
     // TMDS Encoding and Serialization
     wire tmds_ch0_serial, tmds_ch1_serial, tmds_ch2_serial, tmds_chc_serial;
     dvi_generator dvi_out (
@@ -116,18 +116,18 @@ module display_demo_dvi(
         .o_tmds_ch2_serial(tmds_ch2_serial),
         .o_tmds_chc_serial(tmds_chc_serial)  // encode pixel clock via same path
     );
-    
+
     // TMDS Buffered Output
-    OBUFDS #(.IOSTANDARD("TMDS_33")) 
+    OBUFDS #(.IOSTANDARD("TMDS_33"))
         tmds_buf_ch0 (.I(tmds_ch0_serial), .O(hdmi_tx_p[0]), .OB(hdmi_tx_n[0]));
-    OBUFDS #(.IOSTANDARD("TMDS_33")) 
+    OBUFDS #(.IOSTANDARD("TMDS_33"))
         tmds_buf_ch1 (.I(tmds_ch1_serial), .O(hdmi_tx_p[1]), .OB(hdmi_tx_n[1]));
-    OBUFDS #(.IOSTANDARD("TMDS_33")) 
+    OBUFDS #(.IOSTANDARD("TMDS_33"))
         tmds_buf_ch2 (.I(tmds_ch2_serial), .O(hdmi_tx_p[2]), .OB(hdmi_tx_n[2]));
-    OBUFDS #(.IOSTANDARD("TMDS_33")) 
-        tmds_buf_chc (.I(tmds_chc_serial), .O(hdmi_tx_clk_p), .OB(hdmi_tx_clk_n)); 
-      
-    assign hdmi_tx_cec   = 1'bz;        
+    OBUFDS #(.IOSTANDARD("TMDS_33"))
+        tmds_buf_chc (.I(tmds_chc_serial), .O(hdmi_tx_clk_p), .OB(hdmi_tx_clk_n));
+
+    assign hdmi_tx_cec   = 1'bz;
     assign hdmi_tx_rsda  = 1'bz;
     assign hdmi_tx_rscl  = 1'b1;
 endmodule

hdl/demo/display_demo_dvi_pmod3.v

@@ -6,9 +6,9 @@
 // Learn more at https://projectf.io
 
 // This demo requires the following Verilog modules:
-// * display_clocks
-// * display_timings
-// * test_card
+//  * display_clocks
+//  * display_timings
+//  * test_card
 
 module display_demo_dvi_pmod3(
     input  wire CLK,                // board clock: 100 MHz on Arty/Basys3/Nexys
@@ -24,7 +24,7 @@ module display_demo_dvi_pmod3(
 
     wire rst = ~RST_BTN;            // reset is active low on Arty & Nexys Video
     // wire rst = RST_BTN;          // reset is active high on Basys3 (BTNC)
-    
+
     // Display Clocks
     wire pix_clk;                   // pixel clock
     wire clk_lock;                  // clock locked?
@@ -38,10 +38,10 @@ module display_demo_dvi_pmod3(
     )
     display_clocks_inst
     (
-       .i_clk(CLK), 
-       .i_rst(rst), 
-       .o_clk_1x(pix_clk), 
-       .o_clk_5x(),                 // 5x clock not needed for VGA 
+       .i_clk(CLK),
+       .i_rst(rst),
+       .o_clk_1x(pix_clk),
+       .o_clk_5x(),                 // 5x clock not needed for DVI Pmod
        .o_locked(clk_lock)
     );
 
@@ -64,12 +64,12 @@ module display_demo_dvi_pmod3(
         .V_BP(33),                  //      33       23       20        36
         .H_POL(0),                  //       0        1        1         1
         .V_POL(0)                   //       0        1        1         1
-    ) 
-    display_timings_inst (  
+    )
+    display_timings_inst (
         .i_pixclk(pix_clk),
         .i_rst(rst),
-        .o_hs(h_sync), 
-        .o_vs(v_sync), 
+        .o_hs(h_sync),
+        .o_vs(v_sync),
         .o_de(de),
         .o_frame(frame),
         .o_h(),
@@ -81,23 +81,23 @@ module display_demo_dvi_pmod3(
     // Test Card Generation
     wire red, green, blue;
     test_card #(
-        .H_RES(640), 
+        .H_RES(640),
         .V_RES(480)
-    ) 
+    )
     test_card_inst (
         .i_x(x),
         .i_y(y),
         .o_red(red),
         .o_green(green),
         .o_blue(blue)
     );
-    
+
     // 3-bit DVI Output
     assign DVI_HS   = h_sync;
     assign DVI_VS   = v_sync;
     assign DVI_CLK  = pix_clk;
     assign DVI_DE   = de;
-    assign DVI_R    = de & red;         
+    assign DVI_R    = de & red;
     assign DVI_G    = de & green;
     assign DVI_B    = de & blue;
 endmodule