initial code and verilog code generated testing

prateekbashista · Jun 14, 2024 · d285584 · d285584
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commit d285584
Showing 1 changed file with 5 additions and 0 deletions.
diff --git a/generated_verilog/mux.v b/generated_verilog/mux.v
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+module mux(input a, input b, input sel, output ans);
+
+assign ans = sel ? a : b;
+
+endmodule