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AutoVeriL is a program to automate verilog generation of parametrized standard modules, memory blocks and basic digital designs using python and compile verification using iverilog.
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prateekbashista/AutoVeriL---Automated-Verilog-Generation-and-Library
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AutoVeriL is a program to automate verilog generation of parametrized standard modules, memory blocks and basic digital designs using python and compile verification using iverilog.
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