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hal/imxrt106x: fix enet PLL init #601
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agkaminski
previously approved these changes
Oct 2, 2024
nalajcie
previously requested changes
Oct 2, 2024
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please copy the full solution from plo
(setting bypass while changing the PLL freqency)
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- correct clk0 enable bit - add bypass during clock frequency change JIRA: RTOS-507
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agkaminski
approved these changes
Oct 4, 2024
ziemleszcz
approved these changes
Mar 20, 2025
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Description
Fix
_imxrt_ccmInitEnetPll
to correctly initialize enet PLL.Motivation and Context
Enet PLL clk0 is enabled using bit 13 of CCM_ANALOG_PLL_ENET register, but the shift for
enclk0
was 12, which does not match the iMX RT106x RM.Additionally, bypass was needed during the frequency change.
Related: phoenix-rtos/plo#355
Types of changes
How Has This Been Tested?
armv7m7-imxrt106x-evk
.Checklist:
Special treatment