Update README.md

Author: patel-soham

README.md

@@ -1,10 +1,9 @@
 # Dynamic pattern detector using verilog
 A project to implement dynamic pattern detector using verilog in different ways.
-- Dynamic pattern detector with variable number of bits in implicit style fsm which supports APB protocol to configure pattern register value. (COMING SOON)
-- Dynamic 3 bit pattern detector in explicit style fsm.
 - Dynamic pattern detector with variable number of bits in implicit style fsm.
+- Dynamic 3 bit pattern detector in explicit style fsm.
 
 ---
 **Files**
-1. Explicit fsm [design](dynamic_pattern_exp.v) and [testbench](tb_dynamic_pattern_exp.v)
-2. Implicit fsm [design](dynamic_pattern_imp.v) and [testbench](tb_dynamic_pattern_imp.v)
+1. Implicit fsm [design](dynamic_pattern_imp.v) and [testbench](tb_dynamic_pattern_imp.v)
+2. Explicit fsm [design](dynamic_pattern_exp.v) and [testbench](tb_dynamic_pattern_exp.v)