8331281: RISC-V: C2: Support vector-scalar and vector-immediate bitwise logic instructions #18999

zifeihan · 2024-04-29T12:17:58Z

Hi, We want to support vector-scalar and vector-immediate bitwise logic instructions, It was implemented by referring to RVV v1.0 [1]. please take a look and have some reviews. Thanks a lot.
We can use the Int256VectorTests.java[2] to print the compilation log, verify and observe the generation of nodes.

For example, we can use the following command to print the compilation log of a jtreg test case:

/home/zifeihan/jdk-tools/jtreg/bin/jtreg \
-v:default \
-concurrency:16 -timeout:50 \
-javaoption:-XX:+UnlockExperimentalVMOptions \
-javaoption:-XX:+UseRVV \
-javaoption:-XX:+PrintOptoAssembly \
-javaoption:-XX:LogFile=/home/zifeihan/jdk/Int256VectorTests_PrintOptoAssembly.log \
-jdk:/home/zifeihan/jdk/build/linux-riscv64-server-fastdebug/jdk \
/home/zifeihan/jdk/test/jdk/jdk/incubator/vector/Int256VectorTests.java

we can observe the specified compilation log Int256VectorTests_PrintOptoAssembly.log, which contains the vector-scalar and vector-immediate bitwise logic node for the PR implementation.

vand_immI Node

0b4     vloadcon V3	# generate iota indices
0bc     vmla V2, V2, V3, V1
0c4     vand_immI V2, V2, #7
0cc     addi  R7, R30, #16	# ptr, #@addP_reg_imm
0d0     storeV [R7], V2	# vector (rvv)

vor_regI Node

180     vor_regI V1, V1, R30
188     add R31, R14, R31	# ptr, #@addP_reg_reg
18a     addi  R31, R31, #16	# ptr, #@addP_reg_imm
18c     storeV [R31], V1	# vector (rvv)
194     addiw  R11, R11, #8	#@addI_reg_imm
196     blt  R11, R13, B17	#@cmpI_loop  P=0.500000 C=30564.000000

vxor_regI Node

198     vxor_regI V1, V1, R30
1a0     add R14, R16, R14	# ptr, #@addP_reg_reg
1a2     addi  R14, R14, #16	# ptr, #@addP_reg_imm
1a4     storeV [R14], V1	# vector (rvv)
1ac     addiw  R11, R11, #8	#@addI_reg_imm
1ae     blt  R11, R13, B21	#@cmpI_loop  P=0.500000 C=30564.000000

vand_regI_masked Node

234     B31: #	out( B40 B32 ) &lt;- in( B30 )  Freq: 78.5481
234     loadV V2, [R15]	# vector (rvv)
23c     vand_regI_masked V2, V2, R11
244     storeV [R9], V2	# vector (rvv)
24c     mv R10, #8	# int, #@loadConI
24e     ble  R7, R10, B40	#@cmpI_branch  P=0.000001 C=-1.000000

vor_regI_masked Node

1ee     B32: #	out( B38 B33 ) &lt;- in( B31 )  Freq: 75.8475
1ee     loadV V1, [R11]	# vector (rvv)
1f6     vor_regI_masked V1, V1, R31
1fe     addi  R11, R13, #32	# ptr, #@addP_reg_imm
202     bgeu  R29, R10, B38	#@cmpU_branch  P=0.000001 C=-1.000000

vxor_regI_masked Node

1ee     B32: #	out( B38 B33 ) &lt;- in( B31 )  Freq: 75.8475
1ee     loadV V1, [R11]	# vector (rvv)
1f6     vxor_regI_masked V1, V1, R31
1fe     addi  R11, R13, #32	# ptr, #@addP_reg_imm
202     bgeu  R29, R10, B38	#@cmpU_branch  P=0.000001 C=-1.000000

vnotI Node

13c     B23: #	out( B52 B24 ) &lt;- in( B22 )  Freq: 75.1106
13c     loadV V2, [R16]	# vector (rvv)
144     vnotI V2, V2
14c     vand V1, V1, V2
154     bgeu  R9, R12, B52	#@cmpU_branch  P=0.000001 C=-1.000000

vnotI_masked Node

14a     B19: #	out( B22 ) &lt;- in( B18 )  Freq: 0.99999
14a     replicate_imm5 V1, #-3
152     vnotI_masked V1, V1, V0
15a      -- 	// R23=Thread::current(), empty, #@tlsLoadP
15a     mv R31, #0	# int, #@loadConI
15c     j  B22	#@branch

We can test test/jdk/jdk/incubator/vector/Long256VectorTests.java in the same way, and looking at the Opto logs, we will see nodes similar to vand_regL、vor_regL、vxor_regL、vnotL.

vand_regL Node

180     vand_regL V1, V1, R22
188     add R30, R17, R30	# ptr, #@addP_reg_reg
18a     addi  R30, R30, #16	# ptr, #@addP_reg_imm
18c     storeV [R30], V1	# vector (rvv)
194     addiw  R20, R20, #2	#@addI_reg_imm
196     blt  R20, R15, B17	#@cmpI_loop  P=0.500000 C=30564.000000

vor_regL Node

178     loadV V1, [R12]	# vector (rvv)
180     vor_regL V1, V1, R22
188     add R30, R17, R30	# ptr, #@addP_reg_reg
18a     addi  R30, R30, #16	# ptr, #@addP_reg_imm
18c     storeV [R30], V1	# vector (rvv)
194     addiw  R20, R20, #2	#@addI_reg_imm
196     blt  R20, R15, B17	#@cmpI_loop  P=0.500000 C=30564.000000

vxor_regL Node

178     loadV V1, [R12]	# vector (rvv)
180     vxor_regL V1, V1, R22
188     add R30, R17, R30	# ptr, #@addP_reg_reg
18a     addi  R30, R30, #16	# ptr, #@addP_reg_imm
18c     storeV [R30], V1	# vector (rvv)
194     addiw  R20, R20, #2	#@addI_reg_imm
196     blt  R20, R15, B17	#@cmpI_loop  P=0.500000 C=30564.000000

vand_regL_masked Node

1da     B31: #	out( B37 B32 ) &lt;- in( B30 )  Freq: 75.8503
1da     loadV V1, [R31]	# vector (rvv)
1e2     vand_regL_masked V1, V1, R11
1ea     addi  R31, R10, #32	# ptr, #@addP_reg_imm
1ee     bgeu  R30, R29, B37	#@cmpU_branch  P=0.000001 C=-1.000000

vor_regL_masked Node

1da     B31: #	out( B37 B32 ) &lt;- in( B30 )  Freq: 75.8503
1da     loadV V1, [R31]	# vector (rvv)
1e2     vor_regL_masked V1, V1, R11
1ea     addi  R31, R10, #32	# ptr, #@addP_reg_imm
1ee     bgeu  R30, R29, B37	#@cmpU_branch  P=0.000001 C=-1.000000

vxor_regL_masked Node

1da     B31: #	out( B37 B32 ) &lt;- in( B30 )  Freq: 75.8503
1da     loadV V1, [R31]	# vector (rvv)
1e2     vxor_regL_masked V1, V1, R11
1ea     addi  R31, R10, #32	# ptr, #@addP_reg_imm
1ee     bgeu  R30, R29, B37	#@cmpU_branch  P=0.000001 C=-1.000000

vnotL Node

0f4     B17: #	out( B38 B18 ) &lt;- in( B16 )  Freq: 76.238
0f4     # castII of R19, #@castII
0f4     addw  R30, R19, zr	#@convI2L_reg_reg
0f8     slli  R30, R30, (#3 &amp; 0x3f)	#@lShiftL_reg_imm
0fa     add R13, R31, R30	# ptr, #@addP_reg_reg
0fe     addi  R13, R13, #16	# ptr, #@addP_reg_imm
100     loadV V1, [R13]	# vector (rvv)
108     vnotL V1, V1
110     bgeu  R19, R12, B38	#@cmpU_branch  P=0.000001 C=-1.000000

[1] https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc
[2] https://github.com/openjdk/jdk/blob/master/test/jdk/jdk/incubator/vector/Int256VectorTests.java

Testing

Run tier1-3 tests on SOPHON SG2042 (release)
test/jdk/jdk/incubator/vector (fastdebug) qemu 8.1.50 with UseRVV

Progress

Change must be properly reviewed (1 review required, with at least 1 Reviewer)
Change must not contain extraneous whitespace
Commit message must refer to an issue

Issue

JDK-8331281: RISC-V: C2: Support vector-scalar and vector-immediate bitwise logic instructions (Enhancement - P4)

Reviewers

Feilong Jiang (@feilongjiang - Committer)
Fei Yang (@RealFYang - Reviewer)

Reviewing

Using git

Checkout this PR locally:
$ git fetch https://git.openjdk.org/jdk.git pull/18999/head:pull/18999
$ git checkout pull/18999

Update a local copy of the PR:
$ git checkout pull/18999
$ git pull https://git.openjdk.org/jdk.git pull/18999/head

Using Skara CLI tools

Checkout this PR locally:
$ git pr checkout 18999

View PR using the GUI difftool:
$ git pr show -t 18999

Using diff file

Download this PR as a diff file:
https://git.openjdk.org/jdk/pull/18999.diff

Webrev

Link to Webrev Comment

…se logic instructions

bridgekeeper · 2024-04-29T12:18:55Z

👋 Welcome back gcao! A progress list of the required criteria for merging this PR into master will be added to the body of your pull request. There are additional pull request commands available for use with this pull request.

openjdk · 2024-04-29T12:19:29Z

@zifeihan This change now passes all automated pre-integration checks.

ℹ️ This project also has non-automated pre-integration requirements. Please see the file CONTRIBUTING.md for details.

After integration, the commit message for the final commit will be:

8331281: RISC-V: C2: Support vector-scalar and vector-immediate bitwise logic instructions

Reviewed-by: fjiang, fyang

You can use pull request commands such as /summary, /contributor and /issue to adjust it as needed.

At the time when this comment was updated there had been 29 new commits pushed to the master branch:

14198f5: 8329653: JLILaunchTest fails on AIX after JDK-8329131
ae999ea: 8129418: JShell: better highlighting of errors in imports on demand
6422efa: 8332394: Add friendly output when @ir rule missing value
9160ef8: 8332237: [nmt] Remove the need for ThreadStackTracker::track_as_vm()
7c750fd: 8331746: Create a test to verify that the cmm id is not ignored
de57d4b: 8332257: Shenandoah: Move evacuation methods to implementation file
da9c23a: 8325384: sun/security/ssl/SSLSessionImpl/ResumptionUpdateBoundValues.java failing intermittently when main thread is a virtual thread
dc184f1: 8324649: Shenandoah: replace implementation of free set
2599151: 8331202: Support for Duration until another Instant
6f7ddbe: 8260633: [macos] java/awt/dnd/MouseEventAfterStartDragTest/MouseEventAfterStartDragTest.html test failed
... and 19 more: https://git.openjdk.org/jdk/compare/30bb066b1982c5318d54bfe74115306c602e2974...master

As there are no conflicts, your changes will automatically be rebased on top of these commits when integrating. If you prefer to avoid this automatic rebasing, please check the documentation for the /integrate command for further details.

As you do not have Committer status in this project an existing Committer must agree to sponsor your change. Possible candidates are the reviewers of this PR (@feilongjiang, @RealFYang) but any other Committer may sponsor as well.

➡️ To flag this PR as ready for integration with the above commit message, type /integrate in a new comment. (Afterwards, your sponsor types /sponsor in a new comment to perform the integration).

openjdk · 2024-04-29T12:19:45Z

@zifeihan The following label will be automatically applied to this pull request:

hotspot-compiler

When this pull request is ready to be reviewed, an "RFR" email will be sent to the corresponding mailing list. If you would like to change these labels, use the /label pull request command.

mlbridge · 2024-04-30T13:03:15Z

Webrevs

feilongjiang

Overall looks good, with one minor comment.

feilongjiang · 2024-05-11T07:29:46Z

src/hotspot/cpu/riscv/riscv_v.ad

+
+// vector-scalar and (unpredicated)
+
+instruct vand_regI(vReg dst_src, iRegI src) %{


Do we need iRegIorL2I for RegI related instructions?

Thanks for your review. fixed.

feilongjiang

Looks good, thanks!

RealFYang

LGTM.

zifeihan · 2024-05-17T08:53:18Z

@feilongjiang @RealFYang : Thanks for the review.
/integrate

openjdk · 2024-05-17T08:54:34Z

@zifeihan
Your change (at version d83b0b6) is now ready to be sponsored by a Committer.

luhenry · 2024-05-17T13:46:54Z

/sponsor

openjdk · 2024-05-17T13:48:43Z

Going to push as commit e611151.
Since your change was applied there have been 38 commits pushed to the master branch:

44bdf99: 8332239: Improve CSS for block tags
9bb6169: 8317621: --add-script should support JavaScript modules
4eb1eaf: 8329617: Update stylesheet for specs and tool documentation
d4c2edf: 8331855: Convert jdk.jdeps jdeprscan and jdeps to use the Classfile API
beeffd4: 8332109: Convert remaining tests using com.sun.tools.classfile to ClassFile API
e0d1c4b: 8321428: Deprecate for removal the package java.beans.beancontext
0b0445b: 8331724: Refactor j.l.constant implementation to internal package
d84a8fd: 8332327: Return _methods_jmethod_ids field back in VMStructs
f1ce9b0: 8331557: Serial: Refactor SerialHeap::do_collection
14198f5: 8329653: JLILaunchTest fails on AIX after JDK-8329131
... and 28 more: https://git.openjdk.org/jdk/compare/30bb066b1982c5318d54bfe74115306c602e2974...master

Your commit was automatically rebased without conflicts.

openjdk · 2024-05-17T13:48:50Z

@luhenry @zifeihan Pushed as commit e611151.

💡 You may see a message that your pull request was closed with unmerged commits. This can be safely ignored.

8331281: RISC-V: C2: Support vector-scalar and vector-immediate bitwi…

d6d2fd9

…se logic instructions

openjdk bot added the hotspot-compiler hotspot-compiler-dev@openjdk.org label Apr 29, 2024

zifeihan added 3 commits April 30, 2024 14:15

Polishing Code Comment

5c0d64b

Add vand/vor/vxor predicated Node

c085324

Polishing Code comment

a05b204

zifeihan marked this pull request as ready for review April 30, 2024 13:00

openjdk bot added the rfr Pull request is ready for review label Apr 30, 2024

feilongjiang reviewed May 11, 2024

View reviewed changes

Use iRegIorL2I to replace iRegI in AndV/OrVXorV instruct

69c196e

feilongjiang approved these changes May 15, 2024

View reviewed changes

RealFYang approved these changes May 15, 2024

View reviewed changes

openjdk bot added the ready Pull request is ready to be integrated label May 15, 2024

Merge remote-tracking branch 'upstream/master' into JDK-8331281

d83b0b6

openjdk bot added the sponsor Pull request is ready to be sponsored label May 17, 2024

openjdk bot added the integrated Pull request has been integrated label May 17, 2024

openjdk bot closed this May 17, 2024

openjdk bot removed ready Pull request is ready to be integrated rfr Pull request is ready for review sponsor Pull request is ready to be sponsored labels May 17, 2024

RealFYang mentioned this pull request May 24, 2024

8320999: RISC-V: C2 RotateLeftV #19325

Closed

3 tasks

zifeihan deleted the JDK-8331281 branch June 19, 2024 07:04

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

8331281: RISC-V: C2: Support vector-scalar and vector-immediate bitwise logic instructions #18999

8331281: RISC-V: C2: Support vector-scalar and vector-immediate bitwise logic instructions #18999

zifeihan commented Apr 29, 2024 •

edited by openjdk bot

Loading

bridgekeeper bot commented Apr 29, 2024

openjdk bot commented Apr 29, 2024 •

edited

Loading

openjdk bot commented Apr 29, 2024

mlbridge bot commented Apr 30, 2024 •

edited

Loading

feilongjiang left a comment

feilongjiang May 11, 2024

zifeihan May 15, 2024

feilongjiang left a comment

RealFYang left a comment

zifeihan commented May 17, 2024

openjdk bot commented May 17, 2024

luhenry commented May 17, 2024

openjdk bot commented May 17, 2024

openjdk bot commented May 17, 2024


		// vector-scalar and (unpredicated)

		instruct vand_regI(vReg dst_src, iRegI src) %{

8331281: RISC-V: C2: Support vector-scalar and vector-immediate bitwise logic instructions #18999

8331281: RISC-V: C2: Support vector-scalar and vector-immediate bitwise logic instructions #18999

Conversation

zifeihan commented Apr 29, 2024 • edited by openjdk bot Loading

Testing

Progress

Issue

Reviewers

Reviewing

Webrev

bridgekeeper bot commented Apr 29, 2024

openjdk bot commented Apr 29, 2024 • edited Loading

openjdk bot commented Apr 29, 2024

mlbridge bot commented Apr 30, 2024 • edited Loading

Webrevs

feilongjiang left a comment

Choose a reason for hiding this comment

feilongjiang May 11, 2024

Choose a reason for hiding this comment

zifeihan May 15, 2024

Choose a reason for hiding this comment

feilongjiang left a comment

Choose a reason for hiding this comment

RealFYang left a comment

Choose a reason for hiding this comment

zifeihan commented May 17, 2024

openjdk bot commented May 17, 2024

luhenry commented May 17, 2024

openjdk bot commented May 17, 2024

openjdk bot commented May 17, 2024

zifeihan commented Apr 29, 2024 •

edited by openjdk bot

Loading

openjdk bot commented Apr 29, 2024 •

edited

Loading

mlbridge bot commented Apr 30, 2024 •

edited

Loading