-
Notifications
You must be signed in to change notification settings - Fork 5.5k
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
8320999: RISC-V: C2 RotateLeftV #19325
Conversation
/solves JDK-8321000 |
👋 Welcome back mli! A progress list of the required criteria for merging this PR into |
@Hamlin-Li This change now passes all automated pre-integration checks. ℹ️ This project also has non-automated pre-integration requirements. Please see the file CONTRIBUTING.md for details. After integration, the commit message for the final commit will be:
You can use pull request commands such as /summary, /contributor and /issue to adjust it as needed. At the time when this comment was updated there had been 97 new commits pushed to the
As there are no conflicts, your changes will automatically be rebased on top of these commits when integrating. If you prefer to avoid this automatic rebasing, please check the documentation for the /integrate command for further details. ➡️ To integrate this PR with the above commit message to the |
@Hamlin-Li |
@Hamlin-Li The following label will be automatically applied to this pull request:
When this pull request is ready to be reviewed, an "RFR" email will be sent to the corresponding mailing list. If you would like to change these labels, use the /label pull request command. |
Webrevs
|
I'll need to refine the patch a bit, seems imm in vror.vi is 6 bits rather than 5 bits which is the case in basic vector instructions. |
@@ -129,7 +129,7 @@ | |||
|
|||
// Does the CPU supports vector variable shift instructions? | |||
static constexpr bool supports_vector_variable_shifts(void) { | |||
return false; | |||
return true; |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
What's the path to checking for UseZvbb
and UseZvbc
respectively to the specific instruction?
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Here, the 3 checks are not independent, they depend on other checks in both vectorization and vector API, so returning true is fine.
But in order to eliminate everyone’s doubts in the future, I change them return UseZvbb.
I have modified it to use vror.vi with 6 bits imm. |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Hi, I have two comments after a cursory look. Thanks.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Two minor comments remain. Otherwise looks good to me.
BTW: You didn't mention the testing performed. Are these newly-added instructs properly test covered? Thanks.
src/hotspot/cpu/riscv/riscv_v.ad
Outdated
// also supports Byte and Short rotation. But we can still share the intrinsics between vectorization and Vector API. | ||
// | ||
// NOTE: for Long, its valid rotation value is 6 bits, although basic vector instruction only support 5 bit vector-immediate, | ||
// in Zvbb, vror.vi support 6 bits vector-immediate, so the imm implementation of Long and other types can be unified. |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Maybe simply: As vror.vi encodes 6-bits immediate rotate amount, which is different from other vector-immediate instructions, implementation of vector rotation for long and other types can be unified.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
modified
src/hotspot/cpu/riscv/riscv_v.ad
Outdated
|
||
instruct vrotate_right_masked(vReg dst_src, vReg shift, vRegMask_V0 v0) %{ | ||
match(Set dst_src (RotateRightV (Binary dst_src shift) v0)); | ||
effect(TEMP_DEF dst_src); |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Is the TEMP_DEF dst_src
needed for these newly-added masked versions?
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Thanks for catching, removed.
Yes, I've checked the instructs are matched and invoked during tests running. |
Thanks @luhenry @RealFYang for your reviewing. /integrate |
Going to push as commit fed2b56.
Your commit was automatically rebased without conflicts. |
@Hamlin-Li Pushed as commit fed2b56. 💡 You may see a message that your pull request was closed with unmerged commits. This can be safely ignored. |
Hi,
Can you help to review this patch?
More detailed description is inline in the code.
Thanks
Progress
Issues
Reviewers
Reviewing
Using
git
Checkout this PR locally:
$ git fetch https://git.openjdk.org/jdk.git pull/19325/head:pull/19325
$ git checkout pull/19325
Update a local copy of the PR:
$ git checkout pull/19325
$ git pull https://git.openjdk.org/jdk.git pull/19325/head
Using Skara CLI tools
Checkout this PR locally:
$ git pr checkout 19325
View PR using the GUI difftool:
$ git pr show -t 19325
Using diff file
Download this PR as a diff file:
https://git.openjdk.org/jdk/pull/19325.diff
Webrev
Link to Webrev Comment