Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

[rv_dm,dv] Improve modelling of system bringup in ndmreset sequence #24534

Merged
merged 1 commit into from
Oct 1, 2024
Merged

[rv_dm,dv] Improve modelling of system bringup in ndmreset sequence #24534

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
8 changes: 8 additions & 0 deletions hw/ip/rv_dm/dv/env/seq_lib/rv_dm_ndmreset_req_vseq.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -155,6 +155,14 @@ class rv_dm_ndmreset_req_vseq extends rv_dm_base_vseq;
// and then drop the unavailable_i signal to show that the CPU is back. Also behave as lc_ctrl
// and re-enable debug.
cfg.clk_lc_rst_vif.drive_rst_pin(1'b1);

// Debugging should be enabled again (through lc_hw_debug_en), but that will take a short while
// (as the rest of the system comes up). Wait 16 cycles to represent this, which allows rv_dm to
// see the state where the de-asserted LC reset signal has been synchronised (4 cycles) but we
// haven't yet got far enough to allow debug to work again.
//
// Also drop the unavailable_i signal to represent the hart coming back.
cfg.clk_rst_vif.wait_clks(16);
cfg.rv_dm_vif.cb.unavailable <= 0;
lc_hw_debug_en = 1'b1;
upd_lc_hw_debug_en();
Expand Down
Loading