[prim,fpga] Add FPGA-specific primitive implementations for prim_xnor2

It turns out these were missing meaning the FPGA flows fell back to the generic implementation which is not ideal. The same holds for the Yosys synthesis setups where the FPGA primitives are used to get the synthesis constraints. Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
lowRISC · Oct 10, 2024 · 5018ada · 5018ada
1 parent 264c73b
commit 5018ada
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Showing 8 changed files with 120 additions and 1 deletion.
diff --git a/hw/ip/aes/pre_syn/syn_yosys.sh b/hw/ip/aes/pre_syn/syn_yosys.sh
@@ -76,6 +76,7 @@ OT_DEP_SOURCES=(
     "$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_flop_en.sv
     "$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_buf.sv
     "$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_xor2.sv
+    "$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_xnor2.sv
 )
 
 # Get OpenTitan dependency packages.
@@ -115,6 +116,7 @@ for file in "${OT_DEP_SOURCES[@]}"; do
     sed -i 's/prim_buf/prim_xilinx_buf/g'                $LR_SYNTH_OUT_DIR/generated/${module}.v
     sed -i 's/prim_sec_anchor_buf/prim_xilinx_buf/g'     $LR_SYNTH_OUT_DIR/generated/${module}.v
     sed -i 's/prim_xor2/prim_xilinx_xor2/g'              $LR_SYNTH_OUT_DIR/generated/${module}.v
+    sed -i 's/prim_xnor2/prim_xilinx_xnor2/g'            $LR_SYNTH_OUT_DIR/generated/${module}.v
 done
 
 # Rename the prim_sparse_fsm_flop module. For some reason, sv2v decides to append a suffix.
@@ -147,6 +149,7 @@ for file in "$LR_SYNTH_SRC_DIR"/rtl/*.sv; do
     sed -i 's/prim_buf/prim_xilinx_buf/g'                $LR_SYNTH_OUT_DIR/generated/${module}.v
     sed -i 's/prim_sec_anchor_buf/prim_xilinx_buf/g'     $LR_SYNTH_OUT_DIR/generated/${module}.v
     sed -i 's/prim_xor2/prim_xilinx_xor2/g'              $LR_SYNTH_OUT_DIR/generated/${module}.v
+    sed -i 's/prim_xnor2/prim_xilinx_xnor2/g'            $LR_SYNTH_OUT_DIR/generated/${module}.v
 
     # Rename prim_sparse_fsm_flop instances. For some reason, sv2v decides to append a suffix.
     sed -i 's/prim_sparse_fsm_flop_.*/prim_sparse_fsm_flop \#(/g' \

diff --git a/hw/ip/kmac/pre_syn/syn_yosys.sh b/hw/ip/kmac/pre_syn/syn_yosys.sh
@@ -78,6 +78,7 @@ OT_DEP_SOURCES=(
     "$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_flop_en.sv
     "$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_buf.sv
     "$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_xor2.sv
+    "$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_xnor2.sv
     "$LR_SYNTH_SRC_DIR"/../tlul/rtl/tlul_adapter_sram.sv
     "$LR_SYNTH_SRC_DIR"/../tlul/rtl/tlul_sram_byte.sv
     "$LR_SYNTH_SRC_DIR"/../tlul/rtl/tlul_socket_1n.sv
@@ -132,6 +133,7 @@ for file in "${OT_DEP_SOURCES[@]}"; do
     sed -i 's/prim_buf/prim_xilinx_buf/g'                $LR_SYNTH_OUT_DIR/generated/${module}.v
     sed -i 's/prim_sec_anchor_buf/prim_xilinx_buf/g'     $LR_SYNTH_OUT_DIR/generated/${module}.v
     sed -i 's/prim_xor2/prim_xilinx_xor2/g'              $LR_SYNTH_OUT_DIR/generated/${module}.v
+    sed -i 's/prim_xnor2/prim_xilinx_xnor2/g'            $LR_SYNTH_OUT_DIR/generated/${module}.v
 done
 
 # Rename the prim_sparse_fsm_flop module. For some reason, sv2v decides to append a suffix.
@@ -164,6 +166,7 @@ for file in "$LR_SYNTH_SRC_DIR"/rtl/*.sv; do
     sed -i 's/prim_buf/prim_xilinx_buf/g'                $LR_SYNTH_OUT_DIR/generated/${module}.v
     sed -i 's/prim_sec_anchor_buf/prim_xilinx_buf/g'     $LR_SYNTH_OUT_DIR/generated/${module}.v
     sed -i 's/prim_xor2/prim_xilinx_xor2/g'              $LR_SYNTH_OUT_DIR/generated/${module}.v
+    sed -i 's/prim_xnor2/prim_xilinx_xnor2/g'            $LR_SYNTH_OUT_DIR/generated/${module}.v
 
     # Rename prim_sparse_fsm_flop instances. For some reason, sv2v decides to append a suffix.
     sed -i 's/prim_sparse_fsm_flop_.*/prim_sparse_fsm_flop \#(/g' \

diff --git a/hw/ip/otbn/pre_syn/syn_yosys.sh b/hw/ip/otbn/pre_syn/syn_yosys.sh
@@ -77,6 +77,7 @@ OT_DEP_SOURCES=(
     "$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_flop_en.sv
     "$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_buf.sv
     "$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_xor2.sv
+    "$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_xnor2.sv
     "$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_and2.sv
     "$LR_SYNTH_SRC_DIR"/../tlul/rtl/tlul_adapter_sram.sv
     "$LR_SYNTH_SRC_DIR"/../tlul/rtl/tlul_sram_byte.sv
@@ -140,6 +141,7 @@ for file in "${OT_DEP_SOURCES[@]}"; do
     sed -i 's/prim_buf/prim_xilinx_buf/g'                $LR_SYNTH_OUT_DIR/generated/${module}.v
     sed -i 's/prim_sec_anchor_buf/prim_xilinx_buf/g'     $LR_SYNTH_OUT_DIR/generated/${module}.v
     sed -i 's/prim_xor2/prim_xilinx_xor2/g'              $LR_SYNTH_OUT_DIR/generated/${module}.v
+    sed -i 's/prim_xnor2/prim_xilinx_xnor2/g'            $LR_SYNTH_OUT_DIR/generated/${module}.v
     sed -i 's/prim_and2/prim_xilinx_and2/g'              $LR_SYNTH_OUT_DIR/generated/${module}.v
     sed -i 's/prim_ram_1p/prim_generic_ram_1p/g'         $LR_SYNTH_OUT_DIR/generated/${module}.v
 
@@ -177,6 +179,7 @@ for file in "$LR_SYNTH_SRC_DIR"/rtl/*.sv; do
     sed -i 's/prim_buf/prim_xilinx_buf/g'                $LR_SYNTH_OUT_DIR/generated/${module}.v
     sed -i 's/prim_sec_anchor_buf/prim_xilinx_buf/g'     $LR_SYNTH_OUT_DIR/generated/${module}.v
     sed -i 's/prim_xor2/prim_xilinx_xor2/g'              $LR_SYNTH_OUT_DIR/generated/${module}.v
+    sed -i 's/prim_xnor2/prim_xilinx_xnor2/g'            $LR_SYNTH_OUT_DIR/generated/${module}.v
     sed -i 's/prim_and2/prim_xilinx_and2/g'              $LR_SYNTH_OUT_DIR/generated/${module}.v
     sed -i 's/prim_ram_1p/prim_generic_ram_1p/g'         $LR_SYNTH_OUT_DIR/generated/${module}.v
 

diff --git a/hw/ip/prim_generic/rtl/prim_generic_xnor2.sv b/hw/ip/prim_generic/rtl/prim_generic_xnor2.sv
@@ -12,6 +12,6 @@ module prim_generic_xnor2 #(
   output logic [Width-1:0] out_o
 );
 
-  assign out_o = !(in0_i ^ in1_i);
+  assign out_o = ~(in0_i ^ in1_i);
 
 endmodule
diff --git a/hw/ip/prim_xilinx/prim_xilinx_xnor2.core b/hw/ip/prim_xilinx/prim_xilinx_xnor2.core
@@ -0,0 +1,35 @@
+CAPI=2:
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+name: "lowrisc:prim_xilinx:xnor2"
+description: "Xilinx 2-input xnor"
+filesets:
+  files_rtl:
+    files:
+      - rtl/prim_xilinx_xnor2.sv
+    file_type: systemVerilogSource
+
+  files_verilator_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+
+  files_ascentlint_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+
+  files_veriblelint_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+
+targets:
+  default:
+    filesets:
+      - tool_verilator   ? (files_verilator_waiver)
+      - tool_ascentlint  ? (files_ascentlint_waiver)
+      - tool_veriblelint ? (files_veriblelint_waiver)
+      - files_rtl
diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_xnor2.sv b/hw/ip/prim_xilinx/rtl/prim_xilinx_xnor2.sv
@@ -0,0 +1,19 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+`include "prim_assert.sv"
+
+// Prevent Vivado from performing optimizations on/across this module.
+(* DONT_TOUCH = "yes" *)
+module prim_xilinx_xnor2 #(
+  parameter int Width = 1
+) (
+  input [Width-1:0] in0_i,
+  input [Width-1:0] in1_i,
+  output logic [Width-1:0] out_o
+);
+
+  assign out_o = ~(in0_i ^ in1_i);
+
+endmodule
diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_xnor2.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_xnor2.core
@@ -0,0 +1,37 @@
+CAPI=2:
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+name: "lowrisc:prim_xilinx_ultrascale:xnor2"
+description: "Xilinx 2-input xnor"
+filesets:
+  files_rtl:
+    files:
+      - rtl/prim_xilinx_ultrascale_xnor2.sv
+    file_type: systemVerilogSource
+
+  files_verilator_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+    file_type: vlt
+
+  files_ascentlint_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+    file_type: waiver
+
+  files_veriblelint_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+
+targets:
+  default:
+    filesets:
+      - tool_verilator   ? (files_verilator_waiver)
+      - tool_ascentlint  ? (files_ascentlint_waiver)
+      - tool_veriblelint ? (files_veriblelint_waiver)
+      - files_rtl
diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_xnor2.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_xnor2.sv
@@ -0,0 +1,19 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+`include "prim_assert.sv"
+
+// Prevent Vivado from performing optimizations on/across this module.
+(* DONT_TOUCH = "yes" *)
+module prim_xilinx_ultrascale_xnor2 #(
+  parameter int Width = 1
+) (
+  input [Width-1:0] in0_i,
+  input [Width-1:0] in1_i,
+  output logic [Width-1:0] out_o
+);
+
+  assign out_o = ~(in0_i ^ in1_i);
+
+endmodule