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[pre_syn] Fix Yosys synthesis flows for AES, KMAC, OTBN
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During the Earlgrey-PROD tapeout, we decided to introduce the option for
technology specific 2-flop synchronizer cells by converting the
prim_flop_2sync primitive to a generic primitive. This commits aligns
the Yosys synthesis setups with this change.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
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vogelpi committed Oct 10, 2024
1 parent 7e76fe2 commit 264c73b
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Showing 3 changed files with 15 additions and 9 deletions.
8 changes: 5 additions & 3 deletions hw/ip/aes/pre_syn/syn_yosys.sh
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Original file line number Diff line number Diff line change
Expand Up @@ -67,11 +67,11 @@ OT_DEP_SOURCES=(
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_trivium.sv
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_packer_fifo.sv
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_lfsr.sv
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_flop_2sync.sv
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_cdc_rand_delay.sv
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_reg_we_check.sv
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_onehot_check.sv
"$LR_SYNTH_SRC_DIR"/../prim_generic/rtl/prim_generic_flop.sv
"$LR_SYNTH_SRC_DIR"/../prim_generic/rtl/prim_generic_flop_2sync.sv
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_flop.sv
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_flop_en.sv
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_buf.sv
Expand Down Expand Up @@ -109,7 +109,8 @@ for file in "${OT_DEP_SOURCES[@]}"; do
# Make sure auto-generated primitives are resolved to generic or Xilinx-specific primitives
# where available.
sed -i 's/prim_flop/prim_xilinx_flop/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/prim_xilinx_flop_2sync/prim_flop_2sync/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/prim_xilinx_flop_2sync/prim_generic_flop_2sync/g' \
$LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/prim_sec_anchor_flop/prim_xilinx_flop/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/prim_buf/prim_xilinx_buf/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/prim_sec_anchor_buf/prim_xilinx_buf/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
Expand Down Expand Up @@ -140,7 +141,8 @@ for file in "$LR_SYNTH_SRC_DIR"/rtl/*.sv; do
# Make sure auto-generated primitives are resolved to generic or Xilinx-specific primitives
# where available.
sed -i 's/prim_flop/prim_xilinx_flop/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/prim_xilinx_flop_2sync/prim_flop_2sync/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/prim_xilinx_flop_2sync/prim_generic_flop_2sync/g' \
$LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/prim_sec_anchor_flop/prim_xilinx_flop/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/prim_buf/prim_xilinx_buf/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/prim_sec_anchor_buf/prim_xilinx_buf/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
Expand Down
8 changes: 5 additions & 3 deletions hw/ip/kmac/pre_syn/syn_yosys.sh
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Original file line number Diff line number Diff line change
Expand Up @@ -67,13 +67,13 @@ OT_DEP_SOURCES=(
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_trivium.sv
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_packer_fifo.sv
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_lfsr.sv
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_flop_2sync.sv
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_cdc_rand_delay.sv
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_reg_we_check.sv
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_onehot_check.sv
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_mubi4_sender.sv
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_fifo_sync_cnt.sv
"$LR_SYNTH_SRC_DIR"/../prim_generic/rtl/prim_generic_flop.sv
"$LR_SYNTH_SRC_DIR"/../prim_generic/rtl/prim_generic_flop_2sync.sv
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_flop.sv
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_flop_en.sv
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_buf.sv
Expand Down Expand Up @@ -126,7 +126,8 @@ for file in "${OT_DEP_SOURCES[@]}"; do
# Make sure auto-generated primitives are resolved to generic or Xilinx-specific primitives
# where available.
sed -i 's/prim_flop/prim_xilinx_flop/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/prim_xilinx_flop_2sync/prim_flop_2sync/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/prim_xilinx_flop_2sync/prim_generic_flop_2sync/g' \
$LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/prim_sec_anchor_flop/prim_xilinx_flop/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/prim_buf/prim_xilinx_buf/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/prim_sec_anchor_buf/prim_xilinx_buf/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
Expand Down Expand Up @@ -157,7 +158,8 @@ for file in "$LR_SYNTH_SRC_DIR"/rtl/*.sv; do
# Make sure auto-generated primitives are resolved to generic or Xilinx-specific primitives
# where available.
sed -i 's/prim_flop/prim_xilinx_flop/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/prim_xilinx_flop_2sync/prim_flop_2sync/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/prim_xilinx_flop_2sync/prim_generic_flop_2sync/g' \
$LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/prim_sec_anchor_flop/prim_xilinx_flop/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/prim_buf/prim_xilinx_buf/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/prim_sec_anchor_buf/prim_xilinx_buf/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
Expand Down
8 changes: 5 additions & 3 deletions hw/ip/otbn/pre_syn/syn_yosys.sh
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Original file line number Diff line number Diff line change
Expand Up @@ -66,13 +66,13 @@ OT_DEP_SOURCES=(
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_sync_reqack.sv
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_packer_fifo.sv
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_lfsr.sv
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_flop_2sync.sv
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_cdc_rand_delay.sv
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_reg_we_check.sv
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_onehot_check.sv
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_mubi4_sender.sv
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_fifo_sync_cnt.sv
"$LR_SYNTH_SRC_DIR"/../prim_generic/rtl/prim_generic_flop.sv
"$LR_SYNTH_SRC_DIR"/../prim_generic/rtl/prim_generic_flop_2sync.sv
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_flop.sv
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_flop_en.sv
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_buf.sv
Expand Down Expand Up @@ -134,7 +134,8 @@ for file in "${OT_DEP_SOURCES[@]}"; do
# Make sure auto-generated primitives are resolved to generic or Xilinx-specific primitives
# where available.
sed -i 's/prim_flop/prim_xilinx_flop/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/prim_xilinx_flop_2sync/prim_flop_2sync/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/prim_xilinx_flop_2sync/prim_generic_flop_2sync/g' \
$LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/prim_sec_anchor_flop/prim_xilinx_flop/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/prim_buf/prim_xilinx_buf/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/prim_sec_anchor_buf/prim_xilinx_buf/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
Expand Down Expand Up @@ -170,7 +171,8 @@ for file in "$LR_SYNTH_SRC_DIR"/rtl/*.sv; do
# Make sure auto-generated primitives are resolved to generic or Xilinx-specific primitives
# where available.
sed -i 's/prim_flop/prim_xilinx_flop/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/prim_xilinx_flop_2sync/prim_flop_2sync/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/prim_xilinx_flop_2sync/prim_generic_flop_2sync/g' \
$LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/prim_sec_anchor_flop/prim_xilinx_flop/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/prim_buf/prim_xilinx_buf/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/prim_sec_anchor_buf/prim_xilinx_buf/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
Expand Down

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