[topgen] Make toplevel SV and chiplevel templates top-sepcific

This PR makes the toplevel verilog and chiplevel template top-specific
to better scale with multiple tops. This avoids adding multiple cases
to the template dealing with top-specic funcitonality.

Signed-off-by: Robert Schilling <rschilling@rivosinc.com>

hw/top_englishbreakfast/templates/chiplevel.sv.tpl

@@ -0,0 +1 @@
+../../top_earlgrey/templates/chiplevel.sv.tpl

hw/top_englishbreakfast/templates/toplevel.sv.tpl

@@ -0,0 +1 @@
+../../top_earlgrey/templates/toplevel.sv.tpl

util/topgen.py

@@ -14,7 +14,7 @@
 from io import StringIO
 from itertools import chain
 from pathlib import Path
-from typing import Dict, List, Optional, Tuple
+from typing import Dict, List
 
 import hjson
 import tlgen
@@ -1214,16 +1214,19 @@ def render_template(template_path: str, rendered_path: Path,
 //                {seed}
 """.format(top_name=top_name, seed=completecfg["rnd_cnst_seed"])
 
+        # Top and chiplevel templates are top-specific
+        top_template_path = SRCTREE_TOP / "hw" / top_name / "templates"
+
         # SystemVerilog Top:
         # "toplevel.sv.tpl" -> "rtl/autogen/{top_name}.sv"
-        render_template(TOPGEN_TEMPLATE_PATH / "toplevel.sv.tpl",
+        render_template(top_template_path / "toplevel.sv.tpl",
                         out_path / "rtl" / "autogen" / f"{top_name}.sv",
                         gencmd=gencmd)
 
         # Multiple chip-levels (ASIC, FPGA, Verilator, etc)
         for target in topcfg["targets"]:
             target_name = target["name"]
-            render_template(TOPGEN_TEMPLATE_PATH / "chiplevel.sv.tpl",
+            render_template(top_template_path / "chiplevel.sv.tpl",
                             out_path /
                             f"rtl/autogen/chip_{topname}_{target_name}.sv",
                             gencmd=gencmd,