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[TableGen] Fix ordering of register classes. #67245

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Merged
merged 1 commit into from
Sep 24, 2023
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[TableGen] Fix ordering of register classes. #67245

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16 changes: 8 additions & 8 deletions llvm/utils/TableGen/CodeGenRegisters.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1036,8 +1036,8 @@ void CodeGenRegisterClass::computeSubClasses(CodeGenRegBank &RegBank) {
std::optional<std::pair<CodeGenRegisterClass *, CodeGenRegisterClass *>>
CodeGenRegisterClass::getMatchingSubClassWithSubRegs(
CodeGenRegBank &RegBank, const CodeGenSubRegIndex *SubIdx) const {
auto SizeOrder = [this](const CodeGenRegisterClass *A,
const CodeGenRegisterClass *B) {
auto WeakSizeOrder = [this](const CodeGenRegisterClass *A,
const CodeGenRegisterClass *B) {
// If there are multiple, identical register classes, prefer the original
// register class.
if (A == B)
Expand All @@ -1059,7 +1059,7 @@ CodeGenRegisterClass::getMatchingSubClassWithSubRegs(
for (auto &RC : RegClasses)
if (SuperRegRCsBV[RC.EnumValue])
SuperRegRCs.emplace_back(&RC);
llvm::stable_sort(SuperRegRCs, SizeOrder);
llvm::stable_sort(SuperRegRCs, WeakSizeOrder);

assert(SuperRegRCs.front() == BiggestSuperRegRC &&
"Biggest class wasn't first");
Expand All @@ -1072,11 +1072,11 @@ CodeGenRegisterClass::getMatchingSubClassWithSubRegs(
if (SuperRegClassesBV.any())
SuperRegClasses.push_back(std::make_pair(&RC, SuperRegClassesBV));
}
llvm::sort(SuperRegClasses,
[&](const std::pair<CodeGenRegisterClass *, BitVector> &A,
const std::pair<CodeGenRegisterClass *, BitVector> &B) {
return SizeOrder(A.first, B.first);
});
llvm::stable_sort(SuperRegClasses,
[&](const std::pair<CodeGenRegisterClass *, BitVector> &A,
const std::pair<CodeGenRegisterClass *, BitVector> &B) {
return WeakSizeOrder(A.first, B.first);
});

// Find the biggest subclass and subreg class such that R:subidx is in the
// subreg class for all R in subclass.
Expand Down