[RISCV] Fix schedule info for Zqvdotq

[tclin914]

The instructions in Zqvdotq is dot-product operation. So the schedule info should be VIMulAdd rather than VIALU.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

Author: Jim Lin (tclin914)

Changes

The instructions in Zqvdotq is dot-product operation. So the schedule info should be VIMulAdd rather than VIALU.

---

Full diff: https://github.com/llvm/llvm-project/pull/142717.diff

1 Files Affected:

• (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZvqdotq.td (+4-4)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvqdotq.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvqdotq.td
index ea3c53cb0a5dd..27959eaccd904 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvqdotq.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvqdotq.td
@@ -37,11 +37,11 @@ let HasPassthruOp = true, HasMaskOp = true in {
 multiclass VPseudoVQDOT_VV_VX {
   foreach m = MxSet<32>.m in {
     defm "" : VPseudoBinaryV_VV<m>,
-            SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", m.MX,
-                        forcePassthruRead=true>;
+              SchedBinary<"WriteVIMulAddV", "ReadVIMulAddV", "ReadVIMulAddV", m.MX,
+                          forcePassthruRead=true>;
     defm "" : VPseudoBinaryV_VX<m>,
-            SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", m.MX,
-                        forcePassthruRead=true>;
+              SchedBinary<"WriteVIMulAddX", "ReadVIMulAddV", "ReadVIMulAddX", m.MX,
+                          forcePassthruRead=true>;
   }
 }
 

[preames]

These are documented as being for "Vector Single-Width Integer Multiply-Add Instructions", but I see the andes vdot instructions use these. We should probably split out a separate category, but I'm fine with this for now.

[mshockwave]

Agree that we can split out a separate SchedWrite in the future if there is such a need.