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Issues list

[RISCV] Fix masked->unmasked peephole handling masked pseudos with no passthru backend:RISC-V
#122253 opened Jan 9, 2025 by lukel97 Loading…
1
3
[RISCV] Allow non-loop invariant steps in RISCVGatherScatterLowering backend:RISC-V
#122244 opened Jan 9, 2025 by lukel97 Loading…
2
[RISCV] Support vp.{gather,scatter} in RISCVGatherScatterLowering backend:RISC-V
#122232 opened Jan 9, 2025 by lukel97 Loading…
3
[RISCV][CostModel] Add cost for @llvm.experimental.vp.splice backend:RISC-V llvm:analysis
#122223 opened Jan 9, 2025 by LiqinWeng Loading…
2
[RISCV][VLOPT] Add getOperandInfo for integer and floating point widening reductions backend:RISC-V
#122176 opened Jan 8, 2025 by michaelmaitland Loading…
2
[RISCV][VLOPT] Add fp-reductions to getOperandInfo backend:RISC-V
#122151 opened Jan 8, 2025 by michaelmaitland Loading…
2
[LV]Fix max safe elements calculations backend:RISC-V llvm:transforms vectorizers
#122148 opened Jan 8, 2025 by alexey-bataev Loading…
1
[IR][AsmParser] Revamp how floating-point literals work in LLVM IR. backend:AArch64 backend:AMDGPU backend:ARM backend:DirectX backend:Hexagon backend:loongarch backend:NVPTX backend:PowerPC backend:RISC-V backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86 clang:openmp OpenMP related changes to Clang clang Clang issues not falling into any other category debuginfo HLSL HLSL Language Support llvm:analysis llvm:globalisel llvm:instcombine llvm:ir llvm:support llvm:transforms
#121838 opened Jan 6, 2025 by jcranmer-intel Loading…
10
[RISCV] Integrate RISCV target in baremetal toolchain object and deprecate RISCVToolchain object.(3/3) backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category
#121831 opened Jan 6, 2025 by quic-garvgupt Loading…
@quic-garvgupt
3
[RISCV][AArch64] llvm has 9-12% performance degradation compared to gcc for spec2017/500.perlbench_r backend:AArch64 backend:RISC-V
#121813 opened Jan 6, 2025 by michaelmaitland
7
[RISCV][CG]Use processShuffleMasks for per-register shuffles backend:RISC-V backend:X86 llvm:analysis llvm:SelectionDAG SelectionDAGISel as well
#121765 opened Jan 6, 2025 by alexey-bataev Loading…
13
[RISCV] Support [mh]edelegh backend:RISC-V mc Machine (object) code
#121634 opened Jan 4, 2025 by dong-miao Loading…
11
[RISC-V] attribute target arch=+zvkn doesn't add builtins backend:RISC-V clang:headers Headers provided by Clang, e.g. for intrinsics
#121603 opened Jan 3, 2025 by antonblanchard
@4vtomat
2
[RISCV] Fold vector shift of sext/zext to widening multiply backend:RISC-V
#121563 opened Jan 3, 2025 by pfusik Loading…
20
There is no VP intrinsic version of llvm.stepvector? backend:RISC-V vectorizers
#121561 opened Jan 3, 2025 by wangpc-pp
3
[RISCV][NFC] Clarify getRISCVInstructionCost usage backend:RISC-V llvm:analysis
#121556 opened Jan 3, 2025 by arcbbb Loading…
2
Failure to scalarize vp.strided.load backend:RISC-V
#121517 opened Jan 2, 2025 by preames
4
release/19.x: [RISCV] Don't create BuildPairF64 or SplitF64 nodes without D or Zdinx. (#116159) backend:RISC-V
#121501 opened Jan 2, 2025 by topperc Loading… LLVM 19.X Release
2
[AVR] Force relocations for non-encodable jumps backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:loongarch backend:PowerPC backend:RISC-V backend:Sparc backend:SystemZ backend:X86 mc Machine (object) code
#121498 opened Jan 2, 2025 by Patryk27 Loading…
32
[RISCV] Add MIPS extensions backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category
#121394 opened Dec 31, 2024 by djtodoro Loading…
16
[LV][VPlan] Add initial support for CSA vectorization backend:RISC-V llvm:analysis llvm:transforms vectorizers
#121222 opened Dec 27, 2024 by michaelmaitland Loading…
8
[LV]Fix/improve max safe distance analysis backend:RISC-V llvm:analysis llvm:transforms vectorizers
#121156 opened Dec 26, 2024 by alexey-bataev Loading…
10
[RISCV] Emitting proper atomic ABI tag when Zalasr is enabled backend:RISC-V
#121017 opened Dec 24, 2024 by mehnadnerd Loading…
4
[RISCV] Add a generic OOO CPU backend:RISC-V clang Clang issues not falling into any other category
#120712 opened Dec 20, 2024 by wangpc-pp Loading…
11
[RISC-V] Fix incorrect epilogue_begin backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:loongarch backend:m68k backend:MSP430 backend:NVPTX backend:PowerPC backend:RISC-V backend:Sparc backend:SystemZ backend:X86 backend:Xtensa debuginfo
#120623 opened Dec 19, 2024 by RamNalamothu Loading…
1
4
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