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Issues list

[llvm] Fix typos in documentation backend:DirectX backend:RISC-V backend:SPIR-V llvm:binary-utilities
#141078 opened May 22, 2025 by kazutakahirata Loading…
1
[RISCV] Implement base scheduling model for andes 45 series processor. backend:RISC-V
#141008 opened May 22, 2025 by tclin914 Loading…
1
[RISCV][TTI] Implement getPartialReductionCost for the vqdotq cases backend:RISC-V llvm:transforms
#140974 opened May 22, 2025 by preames Loading…
2
[NVPTX] Add syncscope support for cmpxchg backend:ARM backend:NVPTX backend:PowerPC backend:RISC-V
#140812 opened May 20, 2025 by akshayrdeodhar Loading…
@akshayrdeodhar
6
[llvm] annotate interfaces in llvm/ExecutionEngine for DLL export backend:RISC-V
#140809 opened May 20, 2025 by andrurogerz Loading…
1
RISCV: Remove shouldForceRelocation and unneeded relocations backend:RISC-V mc Machine (object) code
#140692 opened May 20, 2025 by MaskRay Loading…
1
[RISCV] Add compress patterns for qc.extu and qc.mvltui backend:RISC-V mc Machine (object) code
#140682 opened May 20, 2025 by hchandel Loading…
5
How to support plenty of RISC-V Custom Instruction Extensions？ backend:RISC-V question A question, not bug report. Check out https://llvm.org/docs/GettingInvolved.html instead!
#140658 opened May 20, 2025 by TJU-PanYizhe
3
[VPlan] Use VPInstructionWithType for uniform casts. backend:RISC-V llvm:transforms vectorizers
#140623 opened May 19, 2025 by fhahn Loading…
1
[VPlan] Simplify branch to scalar ph in VPlan transform. (NFC) backend:PowerPC backend:RISC-V llvm:transforms vectorizers
#140409 opened May 17, 2025 by fhahn Loading…
2
[VPlan] Remove ResumePhi opcode, use regular PHI instead (NFC). backend:PowerPC backend:RISC-V llvm:transforms vectorizers
#140405 opened May 17, 2025 by fhahn Loading…
2
[IR] Add llvm clmul intrinsic backend:RISC-V llvm:ir llvm:SelectionDAG SelectionDAGISel as well
#140301 opened May 16, 2025 by oscardssmith Loading…
73
[RISCV] Support LLVM IR intrinsics for XAndesVDot backend:RISC-V llvm:ir
#140223 opened May 16, 2025 by tclin914 Loading…
5
[VPlan] Connect Entry to scalar preheader during initial construction. backend:PowerPC backend:RISC-V llvm:transforms vectorizers
#140132 opened May 15, 2025 by fhahn Loading…
6
[RISCV] Move RISCVIndirectBranchTracking before Branch Relaxation backend:RISC-V
#139993 opened May 15, 2025 by jaidTw Loading…
5
[RISCV] SiFive CPUs with CLIC CSRs backend:RISC-V question A question, not bug report. Check out https://llvm.org/docs/GettingInvolved.html instead!
#139971 opened May 14, 2025 by lenary
1
[RISCV] Unexpected Latency Pattern for Vector Integer Instructions on Banana Pi BPI-F3 (SpacemiT X60) backend:RISC-V
#139920 opened May 14, 2025 by mikhailramalho
5
[RISCV] Add CodeGen support for Zilsd backend:RISC-V
#139775 opened May 13, 2025 by topperc
@topperc
4
[RISC-V] Allow intrinsics to be used with any pointer type. backend:RISC-V clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category llvm:ir llvm:transforms
#139634 opened May 12, 2025 by hvdijk Loading…
15
release/20.x: [RISCV] Fix assertion failure when using -fstack-clash-protection (#135248) backend:RISC-V
#139388 opened May 10, 2025 by llvmbot Loading… LLVM 20.X Release
2
[RISCV][MC] Add aliases for beq/bne with x0 as the first argument => beqz/bnez backend:RISC-V mc Machine (object) code
#139086 opened May 8, 2025 by asb Loading…
15
[RISCV] Initial support for EarlyCSE backend:RISC-V llvm:transforms
#138812 opened May 7, 2025 by HankChang736 Loading…
7
[llvm] Use *Set::insert_range (NFC) backend:RISC-V llvm:transforms
#138237 opened May 2, 2025 by kazutakahirata Loading…
1
[RISCV][NFC] Refactor Vendor Reloc Declarations backend:RISC-V llvm:binary-utilities
#138226 opened May 2, 2025 by lenary Loading…
6
[RISC-V] infinite loop with -fstack-clash-protection backend:RISC-V
#138130 opened May 1, 2025 by andreas-schwab
4
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