[RISCV] Don't custom lower direct fp_extends where possible #125644
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This avoids lowering scalable fp_extends to _vl nodes that don't need multiple extends (i.e. f16->f32, f32->f64) and adds patterns for them.
Keeping the nodes in their generic SDNode form matches more splat patterns, and also allows us to match vfwred{u,o}sum.vs with a VP reduce and a non-VP fpext (which will show up in EVL tail folding on SPEC CPU 2017)
This replaces most uses the riscv_fpextend_vl_oneuse PatFrag with a more generic one that matches both plain fpextends and riscv_fpextend_vls.
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@llvm/pr-subscribers-backend-risc-v Author: Luke Lau (lukel97) ChangesThis avoids lowering scalable fp_extends to _vl nodes that don't need multiple extends (i.e. f16->f32, f32->f64) and adds patterns for them. Keeping the nodes in their generic SDNode form matches more splat patterns, and also allows us to match vfwred{u,o}sum.vs with a VP reduce and a non-VP fpext (which will show up in EVL tail folding on SPEC CPU 2017) This replaces most uses the riscv_fpextend_vl_oneuse PatFrag with a more generic one that matches both plain fpextends and riscv_fpextend_vls. Patch is 268.04 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/125644.diff 17 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 8e3caf51d876b9..3cef5e5c7180e3 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -9011,6 +9011,10 @@ RISCVTargetLowering::lowerVectorFPExtendOrRoundLike(SDValue Op,
bool IsDirectConv = IsDirectExtend || IsDirectTrunc;
+ // We have regular SD node patterns for direct non-VL extends.
+ if (VT.isScalableVector() && IsDirectConv && !IsVP)
+ return Op;
+
// Prepare any fixed-length vector operands.
MVT ContainerVT = VT;
SDValue Mask, VL;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 268bfe70673a2a..52fe129cef9543 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -776,8 +776,10 @@ class VPseudo<Instruction instr, LMULInfo m, dag outs, dag ins, int sew = 0> :
let SEW = sew;
}
-class GetVTypePredicates<VTypeInfo vti> {
- list<Predicate> Predicates = !cond(!eq(vti.Scalar, f16) : [HasVInstructionsF16],
+class GetVTypePredicates<VTypeInfo vti, bit minimal = false> {
+ list<Predicate> Predicates = !cond(!eq(vti.Scalar, f16) : [!if(minimal,
+ HasVInstructionsF16Minimal,
+ HasVInstructionsF16)],
!eq(vti.Scalar, bf16) : [HasVInstructionsBF16Minimal],
!eq(vti.Scalar, f32) : [HasVInstructionsAnyF],
!eq(vti.Scalar, f64) : [HasVInstructionsF64],
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index 8f77b2ce34d1f1..2047864a3f27d3 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -418,6 +418,21 @@ multiclass VPatWConvertFP2ISDNode_V<SDPatternOperator vop,
}
}
+multiclass VPatWConvertFP2FPSDNode_V<SDPatternOperator vop,
+ list<VTypeInfoToWide> vtis,
+ string instruction_name> {
+ foreach fvtiToFWti = vtis in {
+ defvar fvti = fvtiToFWti.Vti;
+ defvar fwti = fvtiToFWti.Wti;
+ let Predicates = !listconcat(GetVTypePredicates<fvti, minimal=true>.Predicates,
+ GetVTypePredicates<fwti>.Predicates) in
+ def : Pat<(fwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1))),
+ (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_E"#fvti.SEW)
+ (fwti.Vector (IMPLICIT_DEF)),
+ fvti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW, TA_MA)>;
+ }
+}
+
multiclass VPatNConvertI2FPSDNode_W_RM<SDPatternOperator vop,
string instruction_name> {
foreach fvtiToFWti = AllWidenableFloatVectors in {
@@ -536,27 +551,18 @@ multiclass VPatWidenBinaryFPSDNode_VV_VF<SDNode op, string instruction_name> {
defvar wti = vtiToWti.Wti;
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<wti>.Predicates) in {
- def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse
- (vti.Vector vti.RegClass:$rs2),
- (vti.Mask true_mask), (XLenVT srcvalue))),
- (wti.Vector (riscv_fpextend_vl_oneuse
- (vti.Vector vti.RegClass:$rs1),
- (vti.Mask true_mask), (XLenVT srcvalue)))),
+ def : Pat<(op (wti.Vector (riscv_fpextend_oneuse (vti.Vector vti.RegClass:$rs2))),
+ (wti.Vector (riscv_fpextend_oneuse (vti.Vector vti.RegClass:$rs1)))),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
(wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,
vti.RegClass:$rs1, vti.AVL, vti.Log2SEW, TA_MA)>;
- def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse
- (vti.Vector vti.RegClass:$rs2),
- (vti.Mask true_mask), (XLenVT srcvalue))),
- (wti.Vector (riscv_fpextend_vl_oneuse
- (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
- (vti.Mask true_mask), (XLenVT srcvalue)))),
+ def : Pat<(op (wti.Vector (riscv_fpextend_oneuse (vti.Vector vti.RegClass:$rs2))),
+ (wti.Vector (riscv_fpextend_oneuse
+ (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1))))),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
(wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,
vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW, TA_MA)>;
- def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse
- (vti.Vector vti.RegClass:$rs2),
- (vti.Mask true_mask), (XLenVT srcvalue))),
+ def : Pat<(op (wti.Vector (riscv_fpextend_oneuse (vti.Vector vti.RegClass:$rs2))),
(wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
(wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,
@@ -571,12 +577,10 @@ multiclass VPatWidenBinaryFPSDNode_VV_VF_RM<SDNode op, string instruction_name>
defvar wti = vtiToWti.Wti;
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<wti>.Predicates) in {
- def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse
- (vti.Vector vti.RegClass:$rs2),
- (vti.Mask true_mask), (XLenVT srcvalue))),
- (wti.Vector (riscv_fpextend_vl_oneuse
- (vti.Vector vti.RegClass:$rs1),
- (vti.Mask true_mask), (XLenVT srcvalue)))),
+ def : Pat<(op (wti.Vector (riscv_fpextend_oneuse
+ (vti.Vector vti.RegClass:$rs2))),
+ (wti.Vector (riscv_fpextend_oneuse
+ (vti.Vector vti.RegClass:$rs1)))),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_E"#vti.SEW)
(wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,
vti.RegClass:$rs1,
@@ -584,12 +588,10 @@ multiclass VPatWidenBinaryFPSDNode_VV_VF_RM<SDNode op, string instruction_name>
// RISCVInsertReadWriteCSR
FRM_DYN,
vti.AVL, vti.Log2SEW, TA_MA)>;
- def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse
- (vti.Vector vti.RegClass:$rs2),
- (vti.Mask true_mask), (XLenVT srcvalue))),
- (wti.Vector (riscv_fpextend_vl_oneuse
- (vti.Vector (SplatFPOp (vti.Scalar vti.ScalarRegClass:$rs1))),
- (vti.Mask true_mask), (XLenVT srcvalue)))),
+ def : Pat<(op (wti.Vector (riscv_fpextend_oneuse
+ (vti.Vector vti.RegClass:$rs2))),
+ (wti.Vector (riscv_fpextend_oneuse
+ (vti.Vector (SplatFPOp (vti.Scalar vti.ScalarRegClass:$rs1)))))),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_E"#vti.SEW)
(wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,
vti.ScalarRegClass:$rs1,
@@ -597,9 +599,8 @@ multiclass VPatWidenBinaryFPSDNode_VV_VF_RM<SDNode op, string instruction_name>
// RISCVInsertReadWriteCSR
FRM_DYN,
vti.AVL, vti.Log2SEW, TA_MA)>;
- def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse
- (vti.Vector vti.RegClass:$rs2),
- (vti.Mask true_mask), (XLenVT srcvalue))),
+ def : Pat<(op (wti.Vector (riscv_fpextend_oneuse
+ (vti.Vector vti.RegClass:$rs2))),
(wti.Vector (SplatFPOp (fpext_oneuse (vti.Scalar vti.ScalarRegClass:$rs1))))),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_E"#vti.SEW)
(wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,
@@ -619,9 +620,8 @@ multiclass VPatWidenBinaryFPSDNode_WV_WF_RM<SDNode op, string instruction_name>
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<wti>.Predicates) in {
def : Pat<(op (wti.Vector wti.RegClass:$rs2),
- (wti.Vector (riscv_fpextend_vl_oneuse
- (vti.Vector vti.RegClass:$rs1),
- (vti.Mask true_mask), (XLenVT srcvalue)))),
+ (wti.Vector (riscv_fpextend_oneuse
+ (vti.Vector vti.RegClass:$rs1)))),
(!cast<Instruction>(instruction_name#"_WV_"#vti.LMul.MX#"_E"#vti.SEW#"_TIED")
wti.RegClass:$rs2, vti.RegClass:$rs1,
// Value to indicate no rounding mode change in
@@ -630,9 +630,8 @@ multiclass VPatWidenBinaryFPSDNode_WV_WF_RM<SDNode op, string instruction_name>
vti.AVL, vti.Log2SEW,
TAIL_AGNOSTIC)>;
def : Pat<(op (wti.Vector wti.RegClass:$rs2),
- (wti.Vector (riscv_fpextend_vl_oneuse
- (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
- (vti.Mask true_mask), (XLenVT srcvalue)))),
+ (wti.Vector (riscv_fpextend_oneuse
+ (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1))))),
(!cast<Instruction>(instruction_name#"_W"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_E"#vti.SEW)
(wti.Vector (IMPLICIT_DEF)), wti.RegClass:$rs2,
vti.ScalarRegClass:$rs1,
@@ -669,12 +668,10 @@ multiclass VPatWidenFPMulAccSDNode_VV_VF_RM<string instruction_name,
!if(!eq(vti.Scalar, bf16),
[HasStdExtZvfbfwma],
[])) in {
- def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuse
- (vti.Vector vti.RegClass:$rs1),
- (vti.Mask true_mask), (XLenVT srcvalue))),
- (wti.Vector (riscv_fpextend_vl_oneuse
- (vti.Vector vti.RegClass:$rs2),
- (vti.Mask true_mask), (XLenVT srcvalue))),
+ def : Pat<(fma (wti.Vector (riscv_fpextend_oneuse
+ (vti.Vector vti.RegClass:$rs1))),
+ (wti.Vector (riscv_fpextend_oneuse
+ (vti.Vector vti.RegClass:$rs2))),
(wti.Vector wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_VV_"#suffix)
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
@@ -684,9 +681,8 @@ multiclass VPatWidenFPMulAccSDNode_VV_VF_RM<string instruction_name,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fma (wti.Vector (SplatFPOp
(fpext_oneuse (vti.Scalar vti.ScalarRegClass:$rs1)))),
- (wti.Vector (riscv_fpextend_vl_oneuse
- (vti.Vector vti.RegClass:$rs2),
- (vti.Mask true_mask), (XLenVT srcvalue))),
+ (wti.Vector (riscv_fpextend_oneuse
+ (vti.Vector vti.RegClass:$rs2))),
(wti.Vector wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#suffix)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
@@ -705,11 +701,9 @@ multiclass VPatWidenFPNegMulAccSDNode_VV_VF_RM<string instruction_name> {
defvar suffix = vti.LMul.MX # "_E" # vti.SEW;
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<wti>.Predicates) in {
- def : Pat<(fma (fneg (wti.Vector (riscv_fpextend_vl_oneuse
- (vti.Vector vti.RegClass:$rs1),
- (vti.Mask true_mask), (XLenVT srcvalue)))),
- (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
- (vti.Mask true_mask), (XLenVT srcvalue)),
+ def : Pat<(fma (fneg (wti.Vector (riscv_fpextend_oneuse
+ (vti.Vector vti.RegClass:$rs1)))),
+ (riscv_fpextend_oneuse (vti.Vector vti.RegClass:$rs2)),
(fneg wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_VV_"#suffix)
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
@@ -718,9 +712,8 @@ multiclass VPatWidenFPNegMulAccSDNode_VV_VF_RM<string instruction_name> {
FRM_DYN,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fma (SplatFPOp (fpext_oneuse (vti.Scalar vti.ScalarRegClass:$rs1))),
- (fneg (wti.Vector (riscv_fpextend_vl_oneuse
- (vti.Vector vti.RegClass:$rs2),
- (vti.Mask true_mask), (XLenVT srcvalue)))),
+ (fneg (wti.Vector (riscv_fpextend_oneuse
+ (vti.Vector vti.RegClass:$rs2)))),
(fneg wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#suffix)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
@@ -729,8 +722,7 @@ multiclass VPatWidenFPNegMulAccSDNode_VV_VF_RM<string instruction_name> {
FRM_DYN,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fma (fneg (wti.Vector (SplatFPOp (fpext_oneuse (vti.Scalar vti.ScalarRegClass:$rs1))))),
- (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
- (vti.Mask true_mask), (XLenVT srcvalue)),
+ (riscv_fpextend_oneuse (vti.Vector vti.RegClass:$rs2)),
(fneg wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#suffix)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
@@ -749,11 +741,8 @@ multiclass VPatWidenFPMulSacSDNode_VV_VF_RM<string instruction_name> {
defvar suffix = vti.LMul.MX # "_E" # vti.SEW;
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<wti>.Predicates) in {
- def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuse
- (vti.Vector vti.RegClass:$rs1),
- (vti.Mask true_mask), (XLenVT srcvalue))),
- (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
- (vti.Mask true_mask), (XLenVT srcvalue)),
+ def : Pat<(fma (wti.Vector (riscv_fpextend_oneuse (vti.Vector vti.RegClass:$rs1))),
+ (riscv_fpextend_oneuse (vti.Vector vti.RegClass:$rs2)),
(fneg wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_VV_"#suffix)
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
@@ -762,8 +751,7 @@ multiclass VPatWidenFPMulSacSDNode_VV_VF_RM<string instruction_name> {
FRM_DYN,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fma (wti.Vector (SplatFPOp (fpext_oneuse (vti.Scalar vti.ScalarRegClass:$rs1)))),
- (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
- (vti.Mask true_mask), (XLenVT srcvalue)),
+ (riscv_fpextend_oneuse (vti.Vector vti.RegClass:$rs2)),
(fneg wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#suffix)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
@@ -782,11 +770,9 @@ multiclass VPatWidenFPNegMulSacSDNode_VV_VF_RM<string instruction_name> {
defvar suffix = vti.LMul.MX # "_E" # vti.SEW;
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<wti>.Predicates) in {
- def : Pat<(fma (fneg (wti.Vector (riscv_fpextend_vl_oneuse
- (vti.Vector vti.RegClass:$rs1),
- (vti.Mask true_mask), (XLenVT srcvalue)))),
- (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
- (vti.Mask true_mask), (XLenVT srcvalue)),
+ def : Pat<(fma (fneg (wti.Vector (riscv_fpextend_oneuse
+ (vti.Vector vti.RegClass:$rs1)))),
+ (riscv_fpextend_oneuse (vti.Vector vti.RegClass:$rs2)),
wti.RegClass:$rd),
(!cast<Instruction>(instruction_name#"_VV_"#suffix)
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
@@ -795,9 +781,7 @@ multiclass VPatWidenFPNegMulSacSDNode_VV_VF_RM<string instruction_name> {
FRM_DYN,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fma (wti.Vector (SplatFPOp (fpext_oneuse (vti.Scalar vti.ScalarRegClass:$rs1)))),
- (fneg (wti.Vector (riscv_fpextend_vl_oneuse
- (vti.Vector vti.RegClass:$rs2),
- (vti.Mask true_mask), (XLenVT srcvalue)))),
+ (fneg (wti.Vector (riscv_fpextend_oneuse (vti.Vector vti.RegClass:$rs2)))),
wti.RegClass:$rd),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#suffix)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
@@ -806,8 +790,7 @@ multiclass VPatWidenFPNegMulSacSDNode_VV_VF_RM<string instruction_name> {
FRM_DYN,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fma (fneg (wti.Vector (SplatFPOp (fpext_oneuse (vti.Scalar vti.ScalarRegClass:$rs1))))),
- (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
- (vti.Mask true_mask), (XLenVT srcvalue)),
+ (riscv_fpextend_oneuse (vti.Vector vti.RegClass:$rs2)),
wti.RegClass:$rd),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#suffix)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
@@ -1394,6 +1377,8 @@ defm : VPatWConvertFP2ISDNode_V<any_fp_to_sint, "PseudoVFWCVT_RTZ_X_F_V">;
defm : VPatWConvertFP2ISDNode_V<any_fp_to_uint, "PseudoVFWCVT_RTZ_XU_F_V">;
defm : VPatWConvertI2FPSDNode_V<any_sint_to_fp, "PseudoVFWCVT_F_X_V">;
defm : VPatWConvertI2FPSDNode_V<any_uint_to_fp, "PseudoVFWCVT_F_XU_V">;
+defm : VPatWConvertFP2FPSDNode_V<any_fpextend, AllWidenableFloatVectors, "PseudoVFWCVT_F_F_V">;
+defm : VPatWConvertFP2FPSDNode_V<any_fpextend, AllWidenableBFloatToFloatVectors, "PseudoVFWCVTBF16_F_F_V">;
// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
defm : VPatNConvertFP2ISDNode_W<any_fp_to_sint, "PseudoVFNCVT_RTZ_X_F_W">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index f35dc6eb2cb8be..694d210ba8b0f9 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatter...
[truncated]
|
|
How much does this increase RISCVGenDAGISel.inc size. There should be a comment in the file like "Total Array size is 2365123 bytes" |
It goes from 2365123 bytes to 2472466 bytes, mostly because of the PatFrags. I'll see if there's a way to cut it down |
|
I've reworked this to convert the fp_extends to _vl nodes in PreprocessISelDAG so we don't need to add any more patterns. And we can remove the VPatWidenReductionVL_RM patterns too now that we don't need to match fp_extend. |
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This avoids lowering scalable fp_extends that don't need multiple extends (i.e. f16->f32, f32->f64) to _vl nodes, but converts them back during DAG preprocessing so we don't need to add any more patterns.
Keeping the nodes in their generic SDNode form matches more splat patterns