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[AMDGPU] Fix unreachable reg bit width #122107

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merged 11 commits into from
Jan 22, 2025
Merged

[AMDGPU] Fix unreachable reg bit width #122107

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cfbc8ad
fix unreachable reg bit width. need add test case latter
Shoreshen Jan 8, 2025
a083e08
Merge remote-tracking branch 'origin/main' into Add-register-class-bi…
Shoreshen Jan 10, 2025
163fcc1
add test case, hard to find case forind case for SReg_128_XNULL & mer…
Shoreshen Jan 10, 2025
89e1047
fix lit.cfg.py
Shoreshen Jan 10, 2025
b1eddc3
run single pass
Shoreshen Jan 10, 2025
64378c4
fix lit
Shoreshen Jan 10, 2025
61cde04
Merge branch 'llvm:main' into Add-register-class-bit-width-for-SReg_2…
Shoreshen Jan 13, 2025
b971e70
Merge branch 'llvm:main' into Add-register-class-bit-width-for-SReg_2…
Shoreshen Jan 20, 2025
5706df1
Merge branch 'llvm:main' into Add-register-class-bit-width-for-SReg_2…
Shoreshen Jan 21, 2025
6b9cfce
add FIXME in test case
Shoreshen Jan 22, 2025
614c83d
Rename test
arsenm Jan 22, 2025
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fix lit.cfg.py
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@Shoreshen
Shoreshen committed Jan 10, 2025
commit 89e1047bd5b72f0c7604cc5b2ec8da9d3d3c5f4b
2 changes: 1 addition & 1 deletion llvm/test/lit.cfg.py
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Original file line number Diff line number Diff line change
Expand Up @@ -463,7 +463,7 @@ def have_cxx_shared_library():
print("could not exec llvm-readobj")
return False

readobj_out = readobj_cmd.stdout.read().decode("utf-8")
readobj_out = readobj_cmd.stdout.read().decode("ascii")
readobj_cmd.wait()

regex = re.compile(r"(libc\+\+|libstdc\+\+|msvcp).*\.(so|dylib|dll)")
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