[AMDGPU] Fix unreachable reg bit width

[Shoreshen]

Add register class bit width for SReg_256_XNULL and SReg_128_XNULL

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[llvmbot]

@llvm/pr-subscribers-backend-amdgpu

Author: None (Shoreshen)

Changes

Add register class bit width for SReg_256_XNULL and SReg_128_XNULL

---

Full diff: https://github.com/llvm/llvm-project/pull/122107.diff

1 Files Affected:

• (modified) llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp (+2)

diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 319ada3b27bd5a..d9c0aa300855fc 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -2487,6 +2487,7 @@ unsigned getRegBitWidth(unsigned RCID) {
   case AMDGPU::AReg_128_Align2RegClassID:
   case AMDGPU::AV_128RegClassID:
   case AMDGPU::AV_128_Align2RegClassID:
+  case AMDGPU::SReg_128_XNULLRegClassID:
     return 128;
   case AMDGPU::SGPR_160RegClassID:
   case AMDGPU::SReg_160RegClassID:
@@ -2523,6 +2524,7 @@ unsigned getRegBitWidth(unsigned RCID) {
   case AMDGPU::AReg_256_Align2RegClassID:
   case AMDGPU::AV_256RegClassID:
   case AMDGPU::AV_256_Align2RegClassID:
+  case AMDGPU::SReg_256_XNULLRegClassID:
     return 256;
   case AMDGPU::SGPR_288RegClassID:
   case AMDGPU::SReg_288RegClassID:

[arsenm]

Tests?

[Shoreshen]

Tests?

Hi there is another PR depending on this so I created the PR first. Will add tests latter (need to minimize)