[AArch64] Add assembly/disaasembly of atomic ld/st #112892
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This patch adds assembly/disassembly for the following instructions:
- ldfadd{a,al,l,}, ldbfadd{a,al,l,}
- ldfmax{a,al,l,}, ldbfmax{a,al,l,}
- ldfmaxnm{a,al,l,}, ldbfmaxnm{a,al,l,}
- ldfmin{a,al,l,}, ldbfmin{a,al,l,}
- ldfminnm{a,al,l,} ldbfminnm{a,al,l,}
- stfadd{l,}, stbfadd{l,}
- stfmax{l,}, stbfmax{l,}
- stfmaxnm{l,}, stbfmaxnm{l,}
- stfmin{l,}, stbfmin{l,}
- stfminnm{l,}, stbfminnm{l,}
Lukacma
requested review from
jthackray,
momchil-velikov,
CarolineConcatto and
SpencerAbson
|
@llvm/pr-subscribers-mc @llvm/pr-subscribers-backend-aarch64 Author: None (Lukacma) ChangesThis patch adds assembly/disassembly for the following instructions: According to [1] [1]https://developer.arm.com/documentation/ddi0602 Co-authored-by: Spencer Abson [spencer.abson@arm.com](mailto:spencer.abson@arm.com) Patch is 124.71 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/112892.diff 28 Files Affected:
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 1d1d9b5512cfc7..4b24b166143dca 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -12626,3 +12626,64 @@ def : TokenAlias<".H", ".h">;
def : TokenAlias<".S", ".s">;
def : TokenAlias<".D", ".d">;
def : TokenAlias<".Q", ".q">;
+
+//----------------------------------------------------------------------------
+// 2024 Armv9.6 Extensions
+//----------------------------------------------------------------------------
+
+let mayLoad = 1, mayStore = 1 in
+class BaseAtomicFPLoad<RegisterClass regtype, bits<2> sz, bits<2> AR,
+ bits<3> op0, string asm>
+: I<(outs regtype:$Rt),
+ (ins regtype:$Rs, GPR64sp:$Rn),
+ asm, "\t$Rs, $Rt, [$Rn]","", []>,
+ Sched<[]> {
+ bits<5> Rt;
+ bits<5> Rs;
+ bits<5> Rn;
+ let Inst{31-30} = sz;
+ let Inst{29-24} = 0b111100;
+ let Inst{23-22} = AR;
+ let Inst{21} = 0b1;
+ let Inst{20-16} = Rs;
+ let Inst{15} = 0b0;
+ let Inst{14-12} = op0;
+ let Inst{11-10} = 0b00;
+ let Inst{9-5} = Rn;
+ let Inst{4-0} = Rt;
+}
+
+multiclass AtomicFPLoad<bits<2> AR, bits<3> op0, string asm> {
+ def D : BaseAtomicFPLoad<FPR64, 0b11, AR, op0, asm>;
+ def S : BaseAtomicFPLoad<FPR32, 0b10, AR, op0, asm>;
+ def H : BaseAtomicFPLoad<FPR16, 0b01, AR, op0, asm>;
+}
+
+let mayLoad = 1, mayStore = 1 in
+class BaseAtomicFPStore<RegisterClass regtype, bits<2> sz, bit R,
+ bits<3> op0, string asm>
+: I<(outs),
+ (ins regtype:$Rs, GPR64sp:$Rn),
+ asm, "\t$Rs, [$Rn]",
+ "", []>,
+ Sched<[]> {
+ bits<5> Rt;
+ bits<5> Rs;
+ bits<5> Rn;
+ let Inst{31-30} = sz;
+ let Inst{29-23} = 0b1111000;
+ let Inst{22} = R;
+ let Inst{21} = 0b1;
+ let Inst{20-16} = Rs;
+ let Inst{15} = 0b1;
+ let Inst{14-12} = op0;
+ let Inst{11-10} = 0b00;
+ let Inst{9-5} = Rn;
+ let Inst{4-0} = 0b11111;
+}
+
+multiclass AtomicFPStore<bit R, bits<3> op0, string asm> {
+ def D : BaseAtomicFPStore<FPR64, 0b11, R, op0, asm>;
+ def S : BaseAtomicFPStore<FPR32, 0b10, R, op0, asm>;
+ def H : BaseAtomicFPStore<FPR16, 0b01, R, op0, asm>;
+}
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 6c9f0986b9e349..32118992e7e116 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -10378,6 +10378,78 @@ defm : PromoteBinaryv8f16Tov4f32<any_fdiv, FDIVv4f32>;
defm : PromoteBinaryv8f16Tov4f32<any_fmul, FMULv4f32>;
defm : PromoteBinaryv8f16Tov4f32<any_fsub, FSUBv4f32>;
+//===----------------------------===//
+// 2024 Architecture Extensions:
+//===----------------------------===//
+
+let Predicates = [HasLSFE] in {
+ // Floating-point Atomic Load
+ defm LDFADDA : AtomicFPLoad<0b10, 0b000, "ldfadda">;
+ defm LDFADDAL : AtomicFPLoad<0b11, 0b000, "ldfaddal">;
+ defm LDFADD : AtomicFPLoad<0b00, 0b000, "ldfadd">;
+ defm LDFADDL : AtomicFPLoad<0b01, 0b000, "ldfaddl">;
+ defm LDFMAXA : AtomicFPLoad<0b10, 0b100, "ldfmaxa">;
+ defm LDFMAXAL : AtomicFPLoad<0b11, 0b100, "ldfmaxal">;
+ defm LDFMAX : AtomicFPLoad<0b00, 0b100, "ldfmax">;
+ defm LDFMAXL : AtomicFPLoad<0b01, 0b100, "ldfmaxl">;
+ defm LDFMINA : AtomicFPLoad<0b10, 0b101, "ldfmina">;
+ defm LDFMINAL : AtomicFPLoad<0b11, 0b101, "ldfminal">;
+ defm LDFMIN : AtomicFPLoad<0b00, 0b101, "ldfmin">;
+ defm LDFMINL : AtomicFPLoad<0b01, 0b101, "ldfminl">;
+ defm LDFMAXNMA : AtomicFPLoad<0b10, 0b110, "ldfmaxnma">;
+ defm LDFMAXNMAL : AtomicFPLoad<0b11, 0b110, "ldfmaxnmal">;
+ defm LDFMAXNM : AtomicFPLoad<0b00, 0b110, "ldfmaxnm">;
+ defm LDFMAXNML : AtomicFPLoad<0b01, 0b110, "ldfmaxnml">;
+ defm LDFMINNMA : AtomicFPLoad<0b10, 0b111, "ldfminnma">;
+ defm LDFMINNMAL : AtomicFPLoad<0b11, 0b111, "ldfminnmal">;
+ defm LDFMINMN : AtomicFPLoad<0b00, 0b111, "ldfminnm">;
+ defm LDFMINNML : AtomicFPLoad<0b01, 0b111, "ldfminnml">;
+ // BFloat16
+ def LDBFADDA : BaseAtomicFPLoad<FPR16, 0b00, 0b10, 0b000, "ldbfadda">;
+ def LDBFADDAL : BaseAtomicFPLoad<FPR16, 0b00, 0b11, 0b000, "ldbfaddal">;
+ def LDBFADD : BaseAtomicFPLoad<FPR16, 0b00, 0b00, 0b000, "ldbfadd">;
+ def LDBFADDL : BaseAtomicFPLoad<FPR16, 0b00, 0b01, 0b000, "ldbfaddl">;
+ def LDBFMAXA : BaseAtomicFPLoad<FPR16, 0b00, 0b10, 0b100, "ldbfmaxa">;
+ def LDBFMAXAL : BaseAtomicFPLoad<FPR16, 0b00, 0b11, 0b100, "ldbfmaxal">;
+ def LDBFMAX : BaseAtomicFPLoad<FPR16, 0b00, 0b00, 0b100, "ldbfmax">;
+ def LDBFMAXL : BaseAtomicFPLoad<FPR16, 0b00, 0b01, 0b100, "ldbfmaxl">;
+ def LDBFMINA : BaseAtomicFPLoad<FPR16, 0b00, 0b10, 0b101, "ldbfmina">;
+ def LDBFMINAL : BaseAtomicFPLoad<FPR16, 0b00, 0b11, 0b101, "ldbfminal">;
+ def LDBFMIN : BaseAtomicFPLoad<FPR16, 0b00, 0b00, 0b101, "ldbfmin">;
+ def LDBFMINL : BaseAtomicFPLoad<FPR16, 0b00, 0b01, 0b101, "ldbfminl">;
+ def LDBFMAXNMA : BaseAtomicFPLoad<FPR16, 0b00, 0b10, 0b110, "ldbfmaxnma">;
+ def LDBFMAXNMAL : BaseAtomicFPLoad<FPR16, 0b00, 0b11, 0b110, "ldbfmaxnmal">;
+ def LDBFMAXNM : BaseAtomicFPLoad<FPR16, 0b00, 0b00, 0b110, "ldbfmaxnm">;
+ def LDBFMAXNML : BaseAtomicFPLoad<FPR16, 0b00, 0b01, 0b110, "ldbfmaxnml">;
+ def LDBFMINNMA : BaseAtomicFPLoad<FPR16, 0b00, 0b10, 0b111, "ldbfminnma">;
+ def LDBFMINNMAL : BaseAtomicFPLoad<FPR16, 0b00, 0b11, 0b111, "ldbfminnmal">;
+ def LDBFMINNM : BaseAtomicFPLoad<FPR16, 0b00, 0b00, 0b111, "ldbfminnm">;
+ def LDBFMINNML : BaseAtomicFPLoad<FPR16, 0b00, 0b01, 0b111, "ldbfminnml">;
+
+ // Floating-point Atomic Store
+ defm STFADD : AtomicFPStore<0b0, 0b000, "stfadd">;
+ defm STFADDL : AtomicFPStore<0b1, 0b000, "stfaddl">;
+ defm STFMAX : AtomicFPStore<0b0, 0b100, "stfmax">;
+ defm STFMAXL : AtomicFPStore<0b1, 0b100, "stfmaxl">;
+ defm STFMIN : AtomicFPStore<0b0, 0b101, "stfmin">;
+ defm STFMINL : AtomicFPStore<0b1, 0b101, "stfminl">;
+ defm STFMAXNM : AtomicFPStore<0b0, 0b110, "stfmaxnm">;
+ defm STFMAXNML : AtomicFPStore<0b1, 0b110, "stfmaxnml">;
+ defm STFMINNM : AtomicFPStore<0b0, 0b111, "stfminnm">;
+ defm STFMINNML : AtomicFPStore<0b1, 0b111, "stfminnml">;
+ // BFloat16
+ def STBFADD : BaseAtomicFPStore<FPR16, 0b00, 0b0, 0b000, "stbfadd">;
+ def STBFADDL : BaseAtomicFPStore<FPR16, 0b00, 0b1, 0b000, "stbfaddl">;
+ def STBFMAX : BaseAtomicFPStore<FPR16, 0b00, 0b0, 0b100, "stbfmax">;
+ def STBFMAXL : BaseAtomicFPStore<FPR16, 0b00, 0b1, 0b100, "stbfmaxl">;
+ def STBFMIN : BaseAtomicFPStore<FPR16, 0b00, 0b0, 0b101, "stbfmin">;
+ def STBFMINL : BaseAtomicFPStore<FPR16, 0b00, 0b1, 0b101, "stbfminl">;
+ def STBFMAXNM : BaseAtomicFPStore<FPR16, 0b00, 0b0, 0b110, "stbfmaxnm">;
+ def STBFMAXNML : BaseAtomicFPStore<FPR16, 0b00, 0b1, 0b110, "stbfmaxnml">;
+ def STBFMINNM : BaseAtomicFPStore<FPR16, 0b00, 0b0, 0b111, "stbfminnm">;
+ def STBFMINNML : BaseAtomicFPStore<FPR16, 0b00, 0b1, 0b111, "stbfminnml">;
+}
+
include "AArch64InstrAtomics.td"
include "AArch64SVEInstrInfo.td"
include "AArch64SMEInstrInfo.td"
diff --git a/llvm/test/MC/AArch64/LSFE/directive-arch-negative.s b/llvm/test/MC/AArch64/LSFE/directive-arch-negative.s
new file mode 100644
index 00000000000000..2520d777f4cf64
--- /dev/null
+++ b/llvm/test/MC/AArch64/LSFE/directive-arch-negative.s
@@ -0,0 +1,7 @@
+// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
+
+.arch armv9.6-a+lsfe
+.arch armv9.6-a+nolsfe
+ldfadd h0, h1, [x2]
+// CHECK: error: instruction requires: lsfe
+// CHECK: ldfadd h0, h1, [x2]
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/LSFE/directive-arch.s b/llvm/test/MC/AArch64/LSFE/directive-arch.s
new file mode 100644
index 00000000000000..4fd6135e1a5123
--- /dev/null
+++ b/llvm/test/MC/AArch64/LSFE/directive-arch.s
@@ -0,0 +1,5 @@
+// RUN: llvm-mc -triple aarch64 -o - %s 2>&1 | FileCheck %s
+
+.arch armv9.6-a+lsfe
+ldfadd h0, h1, [x2]
+// CHECK: ldfadd h0, h1, [x2]
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/LSFE/directive-arch_extension-negative.s b/llvm/test/MC/AArch64/LSFE/directive-arch_extension-negative.s
new file mode 100644
index 00000000000000..df9850217419c2
--- /dev/null
+++ b/llvm/test/MC/AArch64/LSFE/directive-arch_extension-negative.s
@@ -0,0 +1,6 @@
+// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
+
+.arch_extension lsfe
+.arch_extension nolsfe
+ldfadd h0, h1, [x2]
+// CHECK: ldfadd h0, h1, [x2]
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/LSFE/directive-arch_extension.s b/llvm/test/MC/AArch64/LSFE/directive-arch_extension.s
new file mode 100644
index 00000000000000..1dfca73aeb3403
--- /dev/null
+++ b/llvm/test/MC/AArch64/LSFE/directive-arch_extension.s
@@ -0,0 +1,5 @@
+// RUN: llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
+
+.arch_extension lsfe
+ldfadd h0, h1, [x2]
+// CHECK: ldfadd h0, h1, [x2]
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/LSFE/directive-cpu-negative.s b/llvm/test/MC/AArch64/LSFE/directive-cpu-negative.s
new file mode 100644
index 00000000000000..443161b51e947d
--- /dev/null
+++ b/llvm/test/MC/AArch64/LSFE/directive-cpu-negative.s
@@ -0,0 +1,7 @@
+// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
+
+.cpu generic+lsfe
+.cpu generic+nolsfe
+ldfadd h0, h1, [x2]
+// CHECK: error: instruction requires: lsfe
+// CHECK-NEXT: ldfadd h0, h1, [x2]
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/LSFE/directive-cpu.s b/llvm/test/MC/AArch64/LSFE/directive-cpu.s
new file mode 100644
index 00000000000000..ae58cd67c2c7d4
--- /dev/null
+++ b/llvm/test/MC/AArch64/LSFE/directive-cpu.s
@@ -0,0 +1,5 @@
+// RUN: llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
+
+.cpu generic+lsfe
+ldfadd h0, h1, [x2]
+// CHECK: ldfadd h0, h1, [x2]
diff --git a/llvm/test/MC/AArch64/LSFE/ldfadd-diagnostics.s b/llvm/test/MC/AArch64/LSFE/ldfadd-diagnostics.s
new file mode 100644
index 00000000000000..eb36a0286db7d8
--- /dev/null
+++ b/llvm/test/MC/AArch64/LSFE/ldfadd-diagnostics.s
@@ -0,0 +1,241 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+lsfe 2>&1 < %s| FileCheck %s
+
+//------------------------------------------------------------------------------
+// LDFADD
+//------------------------------------------------------------------------------
+
+ldfadd h0, s2, [x2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldfadd h0, s2, [x2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldfadd s0, d2, [x2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldfadd s0, d2, [x2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldfadd d0, h1, [x2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldfadd d0, h1, [x2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldfadd d0, d1, [w2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldfadd d0, d1, [w2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldfadd s0, s1, [x2, #4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldfadd s0, s1, [x2, #4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// -- ldfadda
+
+ldfadda h0, s2, [x2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldfadda h0, s2, [x2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldfadda s0, d2, [x2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldfadda s0, d2, [x2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldfadda d0, h1, [x2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldfadda d0, h1, [x2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldfadda d0, d1, [w2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldfadda d0, d1, [w2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldfadda s0, s1, [x2, #4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldfadda s0, s1, [x2, #4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// -- ldfaddal
+
+ldfaddal h0, s2, [x2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldfaddal h0, s2, [x2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldfaddal s0, d2, [x2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldfaddal s0, d2, [x2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldfaddal d0, h1, [x2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldfaddal d0, h1, [x2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldfaddal d0, d1, [w2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldfaddal d0, d1, [w2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldfaddal s0, s1, [x2, #4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldfaddal s0, s1, [x2, #4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// -- ldfaddl
+
+ldfaddl h0, s2, [x2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldfaddl h0, s2, [x2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldfaddl s0, d2, [x2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldfaddl s0, d2, [x2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldfaddl d0, h1, [x2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldfaddl d0, h1, [x2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldfaddl d0, d1, [w2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldfaddl d0, d1, [w2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldfaddl s0, s1, [x2, #4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldfaddl s0, s1, [x2, #4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+//------------------------------------------------------------------------------
+// LDBFADD
+//------------------------------------------------------------------------------
+
+ldbfadd s0, h1, [x2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldbfadd s0, h1, [x2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldbfadd h0, s1, [x2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldbfadd h0, s1, [x2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldbfadd s0, s1, [x2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldbfadd s0, s1, [x2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldbfadd d0, d1, [x2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldbfadd d0, d1, [x2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldbfadd h0, h1, [w2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldbfadd h0, h1, [w2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldbfadd h0, h1, [x2, #4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldbfadd h0, h1, [x2, #4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// -- ldbfadda
+
+ldbfadda s0, h1, [x2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldbfadda s0, h1, [x2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldbfadda h0, s1, [x2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldbfadda h0, s1, [x2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldbfadda s0, s1, [x2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldbfadda s0, s1, [x2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldbfadda d0, d1, [x2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldbfadda d0, d1, [x2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldbfadda h0, h1, [w2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldbfadda h0, h1, [w2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldbfadda h0, h1, [x2, #4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldbfadda h0, h1, [x2, #4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// -- ldbfaddal
+
+ldbfaddal s0, h1, [x2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldbfaddal s0, h1, [x2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldbfaddal h0, s1, [x2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldbfaddal h0, s1, [x2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldbfaddal s0, s1, [x2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldbfaddal s0, s1, [x2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldbfaddal d0, d1, [x2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldbfaddal d0, d1, [x2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldbfaddal h0, h1, [w2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldbfaddal h0, h1, [w2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldbfaddal h0, h1, [x2, #4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldbfaddal h0, h1, [x2, #4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// -- ldbfaddl
+
+ldbfaddl s0, h1, [x2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldbfaddl s0, h1, [x2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldbfaddl h0, s1, [x2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldbfaddl h0, s1, [x2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldbfaddl s0, s1, [x2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldbfaddl s0, s1, [x2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldbfaddl d0, d1, [x2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldbfaddl d0, d1, [x2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldbfaddl h0, h1, [w2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldbfaddl h0, h1, [w2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldbfaddl h0, h1, [x2, #4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldbfaddl h0, h1, [x2, #4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/LSFE/ldfadd.s b/llvm/test/MC/AArch64/LSFE/ldfadd.s
new file mode 100644
index 00000000000000..e80ca3b70533af
--- /dev/null
+++ b/llvm/test/MC/AArch64/LSFE/ldfadd.s
@@ -0,0 +1,225 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+lsfe < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+lsfe < %s \
+// RUN: | llvm-objdump -d --mattr=+lsfe - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+lsfe < %s \
+// RUN: | llvm-objdump -d --mattr=-lsfe - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+lsfe < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+lsfe -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+//------------------------------------------------------------------------------
+// LDFADD
+//------------------------------------------------------------------------------
+
+ldfadd h0, h1, [x2]
+// CHECK-INST: ldfadd h0, h1, [x2]
+// CHECK-ENCODING: [0x41,0x00,0x20,0x7c]
+// CHECK-ERROR: instruction requires: lsfe
+// CHECK-UNKNOWN: 7c200041 <unknown>
+
+ldfadd h2, h3, [sp]
+// CHECK-INST: ldfadd h2, h3, [sp]
+// CHECK-ENCODING: [0xe3,0x03,0x22,0x7c]
+// CHECK-ERROR: instruction requires: lsfe
+// CHECK-UNKNOWN: 7c2203e3 <unknown>
+
+ldfadd s0, s1, [x2]
+// CHECK-INST: ldfadd s0, s1, [x2]
+// CHECK-ENCODING: [0x41,0x00,0x20,0xbc]
+// CHECK-ERROR: instruction requires: lsfe
+// CHECK-UNKNOWN: bc200041 <unknown>
+
+ldfadd s2, s3, [sp]
+// CHECK-INST: ldfadd s2, s3, [sp]
+// CHECK-ENCODING: [0xe3,0x03,0x22,0xbc]
+// CHECK-ERR...
[truncated]
|
jthackray
reviewed
Oct 18, 2024
| @@ -10378,6 +10378,78 @@ defm : PromoteBinaryv8f16Tov4f32<any_fdiv, FDIVv4f32>; | |||
| defm : PromoteBinaryv8f16Tov4f32<any_fmul, FMULv4f32>; | |||
| defm : PromoteBinaryv8f16Tov4f32<any_fsub, FSUBv4f32>; | |||
|
|
|||
| //===----------------------------===// | |||
| // 2024 Architecture Extensions: | |||
There was a problem hiding this comment.
Probably worth labelling these as Armv9.6a too, since that's likely to age better.
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
|
|
||
| //------------------------------------------------------------------------------ | ||
| // ldbfmax |
There was a problem hiding this comment.
nit: this comment should be capitalized.
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
|
|
||
| //------------------------------------------------------------------------------ | ||
| // ldbfminnm |
There was a problem hiding this comment.
nit: this comment should be capitalized.
Comment on lines
+12637
to
+12638
| : I<(outs regtype:$Rt), | ||
| (ins regtype:$Rs, GPR64sp:$Rn), |
There was a problem hiding this comment.
Suggested change
| : I<(outs regtype:$Rt), | |
| (ins regtype:$Rs, GPR64sp:$Rn), | |
| : I<(outs regtype:$Rs), | |
| (ins regtype:$Rt, GPR64sp:$Rn), |
|
|
||
| .arch_extension lsfe | ||
| .arch_extension nolsfe | ||
| ldfadd h0, h1, [x2] |
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This patch adds assembly/disassembly for the following instructions:
ldfadd{a,al,l,}, ldbfadd{a,al,l,}
ldfmax{a,al,l,}, ldbfmax{a,al,l,}
ldfmaxnm{a,al,l,}, ldbfmaxnm{a,al,l,}
ldfmin{a,al,l,}, ldbfmin{a,al,l,}
ldfminnm{a,al,l,} ldbfminnm{a,al,l,}
stfadd{l,}, stbfadd{l,}
stfmax{l,}, stbfmax{l,}
stfmaxnm{l,}, stbfmaxnm{l,}
stfmin{l,}, stbfmin{l,}
stfminnm{l,}, stbfminnm{l,}
According to [1]
[1]https://developer.arm.com/documentation/ddi0602
Co-authored-by: Spencer Abson spencer.abson@arm.com
Co-authored-by: Caroline Concatto caroline.concatto@arm.com