Skip to content

Issues: llvm/llvm-project

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Clear current search query, filters, and sorts
729 Open 3,199 Closed
729 Open 3,199 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

[Targets] Migrate from atomic_load_8/16/32/64 to atomic_load_nonext_8/16/32/64. NFC backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:loongarch backend:PowerPC backend:RISC-V backend:Sparc backend:WebAssembly backend:X86
#137428 opened Apr 26, 2025 by topperc Loading…
12
[LLVM][InstCombine] Enable constant folding for SVE asr,lsl and lsr intrinsics. backend:AArch64 llvm:instcombine llvm:transforms
#137350 opened Apr 25, 2025 by paulwalker-arm Loading…
2
[AArch64] Correctly detect X reg from w reg in isCopyImpl backend:AArch64
#137348 opened Apr 25, 2025 by davemgreen Loading…
2
[AArch64] Add FEAT_FPAC to supported CPUs backend:AArch64 clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category
#137330 opened Apr 25, 2025 by jyli0116 Loading…
1
[LLVM][GlobalISel] Ensure G_{F}CONSTANT only store references to scalar Constant{Int,FP}. backend:AArch64 llvm:globalisel
#137319 opened Apr 25, 2025 by paulwalker-arm Loading…
1
DAGCombiner: Support fmaximum/fminimum and fmaximumnum/fminimumnum backend:AArch64 backend:AMDGPU llvm:SelectionDAG SelectionDAGISel as well
#137318 opened Apr 25, 2025 by wzssyqa Loading…
11
IR: Remove uselist for constantdata backend:AArch64 backend:SPIR-V llvm:analysis llvm:instcombine llvm:ir llvm:transforms
#137313 opened Apr 25, 2025 by arsenm Loading…
1
4
[GlobalISel] Clear nsw flags when converting sub to add. backend:AArch64 llvm:globalisel
#137288 opened Apr 25, 2025 by davemgreen Loading…
1
2
AArch64 backend incorrectly lowers mul into umull backend:AArch64 miscompilation
#137274 opened Apr 25, 2025 by vector542
4
integer math miscompile from AArch64 global isel backend backend:AArch64 llvm:globalisel miscompilation
#137254 opened Apr 24, 2025 by regehr
1
2
[AArch64][SME] Split SMECallAttrs out of SMEAttrs backend:AArch64
#137239 opened Apr 24, 2025 by MacDue Loading…
6
[AArch64] Use pattern to select bf16 fpextend backend:AArch64
#137212 opened Apr 24, 2025 by john-brawn-arm Loading…
2
[AArch64] can use XAR for vector rotates where possible backend:AArch64 good first issue https://github.com/llvm/llvm-project/contribute missed-optimization
#137162 opened Apr 24, 2025 by k-arrows
@gxyd
6
[AArch64][SVE] Generate asrd instruction for positive pow-2 divisors … backend:AArch64
#137151 opened Apr 24, 2025 by sushgokh Loading…
6
AArch64: uses store from GP reg where vectorized reg would be better backend:AArch64 missed-optimization
#137086 opened Apr 23, 2025 by MatzeB
4
AArch64: Missed post-increment opportunity backend:AArch64 missed-optimization
#137084 opened Apr 23, 2025 by MatzeB
1
AArch64 SVE: Multiple ptrue instructions not merged backend:AArch64
#137040 opened Apr 23, 2025 by MatzeB
10
[llvm] Add support for llvm IR atomicrmw fminimum/fmaximum instructions backend:AArch64 backend:AMDGPU clang:openmp OpenMP related changes to Clang flang:openmp llvm:globalisel llvm:instcombine llvm:ir llvm:SelectionDAG SelectionDAGISel as well llvm:support llvm:transforms
#136759 opened Apr 22, 2025 by jthackray Loading…
24
fshr-related miscompile by AArch64 backend backend:AArch64 good first issue https://github.com/llvm/llvm-project/contribute llvm:codegen miscompilation
#136746 opened Apr 22, 2025 by regehr
@Ruhung
5
[clang][ARM][AArch64] Don't require arm_acle header for universally defined intrinsics backend:AArch64 backend:ARM backend:X86 clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:headers Headers provided by Clang, e.g. for intrinsics clang Clang issues not falling into any other category
#136742 opened Apr 22, 2025 by sarnex • Draft
9
[GlobalISel] Fix miscompile when narrowing vector load/stores to non-byte-sized types backend:AArch64 llvm:globalisel
#136739 opened Apr 22, 2025 by tobias-stadler Loading…
2
[AArch64] Merge scaled and unscaled narrow zero stores backend:AArch64
#136705 opened Apr 22, 2025 by guy-david Loading…
10
[TTI] Simplify implementation (NFCI) backend:AArch64 backend:AMDGPU backend:ARM backend:DirectX backend:Hexagon backend:loongarch backend:NVPTX backend:PowerPC backend:RISC-V backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86 llvm:analysis
#136674 opened Apr 22, 2025 by s-barannikov Loading…
12
[AArch64] Backend error "Unsupported variadic calling convention" with variadic function with SVE argument backend:AArch64 crash-on-valid generated by fuzzer
#136673 opened Apr 22, 2025 by ostannard
2
[SDAG] Make Select-with-Identity-Fold More Flexible; NFC backend:AArch64 backend:ARM backend:RISC-V backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#136554 opened Apr 21, 2025 by mskamp Loading…
5
ProTip! Type g i on any issue or pull request to go back to the issue listing page.