[M68k] ARII atomic load/store

[knickish]

Only ARI was supported, this PR adds ARII support for atomic loads/stores (also with zero displacement). Closes #107939

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[llvmbot]

@llvm/pr-subscribers-backend-m68k

Author: None (knickish)

Changes

Only ARI was supported, this PR adds ARII support for the basic loads/stores and allows ARII to be selected for atomic loads/stores with zero displacement.

---

Full diff: https://github.com/llvm/llvm-project/pull/108982.diff

3 Files Affected:

• (modified) llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp (+14-2)
• (modified) llvm/lib/Target/M68k/M68kInstrAtomics.td (+7)
• (added) llvm/test/CodeGen/M68k/Atomics/non-ari.ll (+46)

diff --git a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
index dc89fec8108c2d..a6f393bcd8624b 100644
--- a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
+++ b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
@@ -772,6 +772,19 @@ static bool isAddressBase(const SDValue &N) {
   }
 }
 
+static bool AllowARIIWithZeroDisp(SDNode *Parent) {
+  if (!Parent) return false;
+  switch (Parent->getOpcode()) {
+    case ISD::LOAD:
+    case ISD::STORE:
+    case ISD::ATOMIC_LOAD:
+    case ISD::ATOMIC_STORE:
+      return true;
+    default:
+      return false;
+  }
+}
+
 bool M68kDAGToDAGISel::SelectARII(SDNode *Parent, SDValue N, SDValue &Disp,
                                   SDValue &Base, SDValue &Index) {
   M68kISelAddressMode AM(M68kISelAddressMode::AddrType::ARII);
@@ -811,8 +824,7 @@ bool M68kDAGToDAGISel::SelectARII(SDNode *Parent, SDValue N, SDValue &Disp,
   // The idea here is that we want to use AddrType::ARII without displacement
   // only if necessary like memory operations, otherwise this must be lowered
   // into addition
-  if (AM.Disp == 0 && (!Parent || (Parent->getOpcode() != ISD::LOAD &&
-                                   Parent->getOpcode() != ISD::STORE))) {
+  if (AM.Disp == 0 && !AllowARIIWithZeroDisp(Parent)) {
     LLVM_DEBUG(dbgs() << "REJECT: Displacement is Zero\n");
     return false;
   }
diff --git a/llvm/lib/Target/M68k/M68kInstrAtomics.td b/llvm/lib/Target/M68k/M68kInstrAtomics.td
index 84a66253354229..9203a3ef4ed093 100644
--- a/llvm/lib/Target/M68k/M68kInstrAtomics.td
+++ b/llvm/lib/Target/M68k/M68kInstrAtomics.td
@@ -10,9 +10,16 @@ foreach size = [8, 16, 32] in {
   def : Pat<(!cast<SDPatternOperator>("atomic_load_"#size) MxCP_ARI:$ptr),
             (!cast<MxInst>("MOV"#size#"dj") !cast<MxMemOp>("MxARI"#size):$ptr)>;
 
+  def : Pat<(!cast<SDPatternOperator>("atomic_load_"#size) MxCP_ARII:$ptr),
+            (!cast<MxInst>("MOV"#size#"df") !cast<MxMemOp>("MxARII"#size):$ptr)>;
+
   def : Pat<(!cast<SDPatternOperator>("atomic_store_"#size) !cast<MxRegOp>("MxDRD"#size):$val, MxCP_ARI:$ptr),
             (!cast<MxInst>("MOV"#size#"jd") !cast<MxMemOp>("MxARI"#size):$ptr,
                                             !cast<MxRegOp>("MxDRD"#size):$val)>;
+
+  def : Pat<(!cast<SDPatternOperator>("atomic_store_"#size) !cast<MxRegOp>("MxDRD"#size):$val, MxCP_ARII:$ptr),
+            (!cast<MxInst>("MOV"#size#"fd") !cast<MxMemOp>("MxARII"#size):$ptr,
+                                            !cast<MxRegOp>("MxDRD"#size):$val)>;
 }
 
 let Predicates = [AtLeastM68020] in {
diff --git a/llvm/test/CodeGen/M68k/Atomics/non-ari.ll b/llvm/test/CodeGen/M68k/Atomics/non-ari.ll
new file mode 100644
index 00000000000000..1ae545ed87227e
--- /dev/null
+++ b/llvm/test/CodeGen/M68k/Atomics/non-ari.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc %s -o - -mtriple=m68k -mcpu=M68000 | FileCheck %s --check-prefix=NO-ATOMIC
+; RUN: llc %s -o - -mtriple=m68k -mcpu=M68010 | FileCheck %s --check-prefix=NO-ATOMIC
+; RUN: llc %s -o - -mtriple=m68k -mcpu=M68020 | FileCheck %s --check-prefix=ATOMIC
+; RUN: llc %s -o - -mtriple=m68k -mcpu=M68030 | FileCheck %s --check-prefix=ATOMIC
+; RUN: llc %s -o - -mtriple=m68k -mcpu=M68040 | FileCheck %s --check-prefix=ATOMIC
+
+define void @atomic_store_i8_element_monotonic(i8 %val, ptr %base, i32 %offset) nounwind {
+; NO-ATOMIC-LABEL: atomic_store_i8_element_monotonic:
+; NO-ATOMIC:       ; %bb.0:
+; NO-ATOMIC-NEXT:    move.b (7,%sp), %d0
+; NO-ATOMIC-NEXT:    move.l (12,%sp), %d1
+; NO-ATOMIC-NEXT:    move.l (8,%sp), %a0
+; NO-ATOMIC-NEXT:    move.b %d0, (0,%a0,%d1)
+; NO-ATOMIC-NEXT:    rts
+;
+; ATOMIC-LABEL: atomic_store_i8_element_monotonic:
+; ATOMIC:       ; %bb.0:
+; ATOMIC-NEXT:    move.b (7,%sp), %d0
+; ATOMIC-NEXT:    move.l (12,%sp), %d1
+; ATOMIC-NEXT:    move.l (8,%sp), %a0
+; ATOMIC-NEXT:    move.b %d0, (0,%a0,%d1)
+; ATOMIC-NEXT:    rts
+  %store_pointer = getelementptr i8, ptr %base, i32 %offset
+  store atomic i8 %val, ptr %store_pointer monotonic, align 1
+  ret void
+}
+
+define i8 @atomic_load_i8_element_monotonic(ptr %base, i32 %offset) nounwind {
+; NO-ATOMIC-LABEL: atomic_load_i8_element_monotonic:
+; NO-ATOMIC:       ; %bb.0:
+; NO-ATOMIC-NEXT:    move.l (8,%sp), %d0
+; NO-ATOMIC-NEXT:    move.l (4,%sp), %a0
+; NO-ATOMIC-NEXT:    move.b (0,%a0,%d0), %d0
+; NO-ATOMIC-NEXT:    rts
+;
+; ATOMIC-LABEL: atomic_load_i8_element_monotonic:
+; ATOMIC:       ; %bb.0:
+; ATOMIC-NEXT:    move.l (8,%sp), %d0
+; ATOMIC-NEXT:    move.l (4,%sp), %a0
+; ATOMIC-NEXT:    move.b (0,%a0,%d0), %d0
+; ATOMIC-NEXT:    rts
+  %load_pointer = getelementptr i8, ptr %base, i32 %offset
+  %return_val = load atomic i8, ptr %load_pointer monotonic, align 1
+  ret i8 %return_val
+}

[github-actions]

✅ With the latest revision this PR passed the C/C++ code formatter.

[knickish]

Ping @mshockwave

[knickish]

Ping @0x59616e maybe? Are there any other reviewers who would be better to ask?

[0x59616e]

LGTM!

[github-actions]

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