[AMDGPU] Add MachineVerifier check to detect illegal copies from vector register to SGPR #105494

AditiRM · 2024-08-21T10:09:25Z

Addition of a check in the MachineVerifier to detect and report illegal vector registers to SGPR copies in the AMDGPU backend, ensuring correct code generation.
We can enforce this check only after SIFixSGPRCopies pass.
This is half-fix in the pipeline with the help of isSSA MachineFuction property, the check is happening for passes after phi-node-elimination.

…to SGPR

llvmbot · 2024-08-21T10:09:44Z

@llvm/pr-subscribers-backend-amdgpu

Author: Aditi Medhane (AditiRM)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/105494.diff

6 Files Affected:

(modified) llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (+29-3)
(modified) llvm/lib/Target/AMDGPU/SIInstrInfo.h (+3)
(added) llvm/test/CodeGen/AMDGPU/fix-illegal-vgpr-copies.mir (+29)
(added) llvm/test/CodeGen/AMDGPU/phi-moveimm-subreg-input.mir (+30)
(modified) llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir (-32)
(modified) llvm/test/CodeGen/AMDGPU/wqm.mir (+4-5)

diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index b6dd4905fb61bb..22572a92227b70 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4613,15 +4613,41 @@ static bool isSubRegOf(const SIRegisterInfo &TRI,
          SubReg.getReg() == SuperVec.getReg();
 }
 
+// Verify the illgal copy from VGPR to SGPR for generic opcode COPY
+bool SIInstrInfo::verifyCopy(const MachineInstr &MI,
+                             const MachineRegisterInfo &MRI,
+                             StringRef &ErrInfo) const {
+  const MachineOperand &Dst = MI.getOperand(0);
+  const MachineOperand &Src = MI.getOperand(1);
+
+  if (Dst.isReg() && Src.isReg()) {
+    Register DstReg = Dst.getReg();
+    Register SrcReg = Src.getReg();
+    // This is a check for copy from an VGPR to SGPR
+    if (RI.isVGPR(MRI, SrcReg) && RI.isSGPRReg(MRI, DstReg)) {
+      ErrInfo = "illegal copy from VGPR to SGPR";
+      return false;
+    }
+  }
+  return true;
+}
+
 bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
                                     StringRef &ErrInfo) const {
   uint16_t Opcode = MI.getOpcode();
-  if (SIInstrInfo::isGenericOpcode(MI.getOpcode()))
-    return true;
-
   const MachineFunction *MF = MI.getParent()->getParent();
   const MachineRegisterInfo &MRI = MF->getRegInfo();
 
+  if (SIInstrInfo::isGenericOpcode(MI.getOpcode())) {
+    // FIXME: At this point the COPY verify is done only for non-ssa forms.
+    // Find a better property to recognize the point where instruction selection
+    // is just done.
+    if (!MRI.isSSA() && MI.isCopy())
+      return verifyCopy(MI, MRI, ErrInfo);
+    
+    return true;
+  }
+
   int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
   int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
   int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 1712dfe8d406cc..4caf37cd2f08e0 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -178,6 +178,9 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
 
   Register findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
 
+  bool verifyCopy(const MachineInstr &MI, const MachineRegisterInfo &MRI,
+                  StringRef &ErrInfo) const;
+
 protected:
   /// If the specific machine instruction is a instruction that moves/copies
   /// value from one register to another register return destination and source
diff --git a/llvm/test/CodeGen/AMDGPU/fix-illegal-vgpr-copies.mir b/llvm/test/CodeGen/AMDGPU/fix-illegal-vgpr-copies.mir
new file mode 100644
index 00000000000000..8eaab0a16e55e4
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/fix-illegal-vgpr-copies.mir
@@ -0,0 +1,29 @@
+# RUN: not --crash llc -march=amdgcn -mcpu=gfx1200 -run-pass=machineverifier %s 2>&1 | FileCheck -check-prefix=ERR %s
+
+---
+name: fix-illegal-copies
+tracksRegLiveness: true
+machineFunctionInfo:
+  isEntryFunction: true
+body:             |
+  bb.0:
+    %0:vgpr_32 = IMPLICIT_DEF
+    %0:vgpr_32 = IMPLICIT_DEF ; Break SSA format
+    %1:vgpr_32 = IMPLICIT_DEF
+    %2:sgpr_32 = IMPLICIT_DEF
+    %3:sgpr_32 = IMPLICIT_DEF
+
+    ; ERR: *** Bad machine code: illegal copy from VGPR to SGPR ***
+    ; ERR: instruction: %4:sgpr_32 = COPY %0:vgpr_32
+    %4:sgpr_32 = COPY %0:vgpr_32
+
+    ; ERR: *** Bad machine code: illegal copy from VGPR to SGPR ***
+    ; ERR: instruction: $sgpr0 = COPY %0:vgpr_32
+    $sgpr0 = COPY %0:vgpr_32
+    
+    ; ERR: *** Bad machine code: illegal copy from VGPR to SGPR ***
+    ; ERR: instruction: $sgpr1 = COPY $vgpr0
+    $sgpr1 = COPY $vgpr0
+
+    S_ENDPGM 0
+...
diff --git a/llvm/test/CodeGen/AMDGPU/phi-moveimm-subreg-input.mir b/llvm/test/CodeGen/AMDGPU/phi-moveimm-subreg-input.mir
new file mode 100644
index 00000000000000..5d58673f7bdca9
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/phi-moveimm-subreg-input.mir
@@ -0,0 +1,30 @@
+# RUN: not --crash llc  -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=si-fix-sgpr-copies -o - %s 2>&1 | FileCheck -check-prefix=GCN %s
+
+# GCN: *** Bad machine code: illegal copy from VGPR to SGPR ***
+# GCN: instruction: undef %5.sub0:sreg_64 = COPY %0:vgpr_32
+name:            phi_moveimm_subreg_input
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    successors: %bb.1
+    liveins: $sgpr0, $sgpr1
+
+    %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+
+    %4:sreg_32 = COPY $sgpr0
+    %5:sreg_32 = COPY $sgpr1
+
+  bb.1:
+    successors: %bb.2
+    undef %2.sub0:sreg_64 = S_ADD_U32 %4, %5, implicit-def $scc
+    S_BRANCH %bb.2
+
+  bb.2:
+    successors: %bb.3
+    %3:sreg_64 = PHI %1, %bb.3, %2, %bb.1
+    S_BRANCH %bb.3
+
+  bb.3:
+    successors: %bb.2
+    undef %1.sub0:sreg_64 = COPY %0
+    S_BRANCH %bb.2
diff --git a/llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir b/llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir
index f931acb8408da2..2b78f984ae775c 100644
--- a/llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir
+++ b/llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir
@@ -32,38 +32,6 @@ body:             |
     S_BRANCH %bb.2
 ...
 
----
-# GCN-LABEL: name: phi_moveimm_subreg_input
-# GCN: %{{[0-9]+}}:sreg_64 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
-name:            phi_moveimm_subreg_input
-tracksRegLiveness: true
-body:             |
-  bb.0:
-    successors: %bb.1
-    liveins: $sgpr0, $sgpr1
-
-    %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-
-    %4:sreg_32 = COPY $sgpr0
-    %5:sreg_32 = COPY $sgpr1
-
-  bb.1:
-    successors: %bb.2
-    undef %2.sub0:sreg_64 = S_ADD_U32 %4, %5, implicit-def $scc
-    S_BRANCH %bb.2
-
-  bb.2:
-    successors: %bb.3
-    %3:sreg_64 = PHI %1, %bb.3, %2, %bb.1
-    S_BRANCH %bb.3
-
-  bb.3:
-    successors: %bb.2
-    undef %1.sub0:sreg_64 = COPY %0
-    S_BRANCH %bb.2
-...
-
-
 ---
 # GCN-LABEL: name: phi_moveimm_bad_opcode_input
 # GCN-NOT: %{{[0-9]+}}:sreg_32 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
diff --git a/llvm/test/CodeGen/AMDGPU/wqm.mir b/llvm/test/CodeGen/AMDGPU/wqm.mir
index ef6d0780f395fd..5ff508b1e3842e 100644
--- a/llvm/test/CodeGen/AMDGPU/wqm.mir
+++ b/llvm/test/CodeGen/AMDGPU/wqm.mir
@@ -189,9 +189,9 @@ body:             |
 # Ensure that strict_wwm is not put around an EXEC copy
 #CHECK-LABEL: name: copy_exec
 #CHECK: %7:sreg_64 = COPY $exec
-#CHECK-NEXT: %14:sreg_64 = ENTER_STRICT_WWM -1, implicit-def $exec, implicit-def $scc, implicit $exec
+#CHECK-NEXT: %13:sreg_64 = ENTER_STRICT_WWM -1, implicit-def $exec, implicit-def $scc, implicit $exec
 #CHECK-NEXT: %8:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-#CHECK-NEXT: $exec = EXIT_STRICT_WWM %14
+#CHECK-NEXT: $exec = EXIT_STRICT_WWM %13
 #CHECK-NEXT: %9:vgpr_32 = V_MBCNT_LO_U32_B32_e64 %7.sub0, 0, implicit $exec
 name:            copy_exec
 tracksRegLiveness: true
@@ -212,10 +212,9 @@ body:             |
     %10:vgpr_32 = V_MBCNT_LO_U32_B32_e64 %8.sub0:sreg_64, 0, implicit $exec
     %11:vgpr_32 = V_MOV_B32_dpp %9:vgpr_32, %10:vgpr_32, 312, 15, 15, 0, implicit $exec
     %12:sreg_32 = V_READLANE_B32 %11:vgpr_32, 63
-    early-clobber %13:sreg_32 = STRICT_WWM %9:vgpr_32, implicit $exec
+    early-clobber %13:vgpr_32 = STRICT_WWM %9:vgpr_32, implicit $exec
 
-    %14:vgpr_32 = COPY %13
-    BUFFER_STORE_DWORD_OFFSET_exact killed %14, %4, %5, 4, 0, 0, implicit $exec
+    BUFFER_STORE_DWORD_OFFSET_exact killed %13, %4, %5, 4, 0, 0, implicit $exec
     S_ENDPGM 0
 
 ...

github-actions · 2024-08-21T10:13:59Z

✅ With the latest revision this PR passed the C/C++ code formatter.

jayfoad · 2024-08-21T10:22:21Z

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

+    // FIXME: At this point the COPY verify is done only for non-ssa forms.
+    // Find a better property to recognize the point where instruction selection
+    // is just done.
+    if (!MRI.isSSA() && MI.isCopy())


Why is the isSSA check needed?

Because we lack the appropriate property to express the real condition, and this is a half measure. We really want a custom IsSelectedAndSGPRCopiesFixed property, otherwise the natural check will fail before SIFixSGPRCopies

OK, then the comment should say explicitly say that we can only enforce this after SIFixSGPRCopies.

I was wondering; the existing MachineFunctionProperties::Property::Selected currently set in the GISel pipeline when selection is completed, should be set in the SelectionDAG as well (mostly after finalize-isel) for consistency. MachineFunctions currently don't have this property set for SelectionDAG.
If this field is rightly set, we could catch the illegal copies soon after finalize-isel, by then SIFixSGPRCopies would have been invoked.

The problem is if selectiondag sets it, the natural place it would be set in selection is still before SIFixSGPRCopies

Isn't FinalizeISel that marks the end of selection? If not, the pass name is misleading.

Yes and no, and I don't think it's really misleading. It finalizes the already selected function into a verifiable form.

Improve the comment to include Jay's suggestion.
"explicitly say that we can only enforce this after SIFixSGPRCopies."

Improved the comment.

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

llvm/test/CodeGen/AMDGPU/fix-illegal-vgpr-copies.mir

llvm/test/CodeGen/AMDGPU/phi-moveimm-subreg-input.mir

Addition of illegal AGPR to SGPR copies and update with review changes

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

cdevadas · 2024-08-27T11:09:03Z

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

+    // FIXME: At this point the COPY verify is done only for non-ssa forms.
+    // Find a better property to recognize the point where instruction selection
+    // is just done.
+    if (!MRI.isSSA() && MI.isCopy())


Improve the comment to include Jay's suggestion.
"explicitly say that we can only enforce this after SIFixSGPRCopies."

llvm/test/CodeGen/AMDGPU/phi-moveimm-subreg-input.mir

llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir

cdevadas · 2024-08-27T11:18:47Z

Change the PR heading and the description to include vector register instead of VGPR.

introduced vector register illegal copies for both VGPR and AGPR, removed subreg-input testcase scenario, updated the testcase error checks accordingly

cdevadas

LGTM

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

llvm/test/MachineVerifier/fix-illegal-copies.mir

arsenm · 2024-08-28T17:30:10Z

llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir

-
-  bb.3:
-    successors: %bb.2
-    undef %1.sub0:sreg_64 = COPY %0


Can you move the sub register indices to the phi input operands, instead of deleting the test

Updated the testcase. Please check @arsenm.

Removed the redundancy of isGenericOpcode check, now isCopy check is indepenent of Generic Opcodes (GISEL pipeline) & SDAG piepeline

Move the AMDGPU target specific testcases in MachineVerifier separately into new directory. Reference : #105494 (comment)

arsenm · 2024-09-06T12:51:09Z

llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir

    S_BRANCH %bb.2

  bb.2:
    successors: %bb.3
-    %3:sreg_64 = PHI %1, %bb.3, %2, %bb.1
+    %3:sreg_32 = PHI %1, %bb.3, %2, %bb.1


%1 should probably be a full copy, and this operand %1.sub0 (same for %2)

Can you please explain why you think we should be introducing subreg in PHI input itself?
The current modified testcase is retaining the original intention of previous testcase.

When the phi is being processed, the only relevant sub registers would come from the phi's own operands, not some other instructions

…08389) - Updated `phi_moveimm_subreg_input` test case to introduce sub-registers as PHI input operands. Currently subreg is making the testcase in non-SSA format, need to fix this by giving subreg as an input operand to PHI instead defining the subreg register. This change is relevant for : [[AMDGPU] Add MachineVerifier check to detect illegal copies from vector register to SGPR ](#105494)

cdevadas · 2024-09-19T05:25:12Z

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

+  if (!MRI.isSSA() && MI.isCopy())
+    return verifyCopy(MI, MRI, ErrInfo);
+
+  if (SIInstrInfo::isGenericOpcode(MI.getOpcode())) {


No need of braces.

cdevadas · 2024-09-19T05:29:15Z

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

+  // FIXME: At this point the COPY verify is done only for non-ssa forms.
+  // Find a better property to recognize the point where instruction selection
+  // is just done.
+  // We can only enforce this check after SIFixSGPRCopies pass.


The last sentence is incomplete. May be, something like the following:
We can only enforce this check after SIFixSGPRCopies so that the illegal copies are legalized and thereafter we don't expect a pass inserting similar copies.

cdevadas · 2024-09-19T09:22:07Z

llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir

@@ -112,7 +112,6 @@ body:             |
    S_BRANCH %bb.2
 ...

-


Unwanted diff. This file shouldn't have any change now.

…or register to SGPR (llvm#105494) Addition of a check in the MachineVerifier to detect and report illegal vector registers to SGPR copies in the AMDGPU backend, ensuring correct code generation. We can enforce this check only after SIFixSGPRCopies pass. This is half-fix in the pipeline with the help of isSSA MachineFuction property, the check is happening for passes after phi-node-elimination.

llvm-ci · 2024-09-20T06:17:28Z

LLVM Buildbot has detected a new failure on builder llvm-clang-x86_64-expensive-checks-debian running on gribozavr4 while building llvm at step 6 "test-build-unified-tree-check-all".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/16/builds/5632

Here is the relevant piece of the build log for the reference

Step 6 (test-build-unified-tree-check-all) failure: test (failure)
******************** TEST 'LLVM :: CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll' FAILED ********************
Exit Code: 1

Command Output (stderr):
--
RUN: at line 1: not /b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc -mtriple=amdgcn < /b/1/llvm-clang-x86_64-expensive-checks-debian/llvm-project/llvm/test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll 2>&1 | /b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/FileCheck -check-prefix=ERR /b/1/llvm-clang-x86_64-expensive-checks-debian/llvm-project/llvm/test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll
+ not /b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc -mtriple=amdgcn
+ /b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/FileCheck -check-prefix=ERR /b/1/llvm-clang-x86_64-expensive-checks-debian/llvm-project/llvm/test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll
/b/1/llvm-clang-x86_64-expensive-checks-debian/llvm-project/llvm/test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll:4:8: error: ERR: expected string not found in input
; ERR: error: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_i32 void (): illegal VGPR to SGPR copy
       ^
<stdin>:1:1: note: scanning from here

^

Input file: <stdin>
Check file: /b/1/llvm-clang-x86_64-expensive-checks-debian/llvm-project/llvm/test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll

-dump-input=help explains the following input dump.

Input was:
<<<<<<
         1:  
check:4     X error: no match found
         2: # After Eliminate PHI nodes for register allocation 
check:4     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
         3: # Machine code for function illegal_vgpr_to_sgpr_copy_i32: NoPHIs, TracksLiveness 
check:4     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
         4:  
check:4     ~
         5: bb.0 (%ir-block.0): 
check:4     ~~~~~~~~~~~~~~~~~~~~
         6:  INLINEASM &"; def $0" [sideeffect] [attdialect], $0:[regdef], implicit-def $vgpr1 
check:4     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
         .
         .
         .
>>>>>>

--

********************

arsenm · 2024-09-20T06:27:53Z

LLVM Buildbot has detected a new failure on builder llvm-clang-x86_64-expensive-checks-debian running on gribozavr4 while building llvm at step 6 "test-build-unified-tree-check-all".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/16/builds/5632

Here is the relevant piece of the build log for the reference

Fixed f9bd083

[AMDGPU] Add MachineVerifer check to detect illegal copies from VGPR …

28724d6

…to SGPR

AditiRM added the backend:AMDGPU label Aug 21, 2024

AditiRM requested review from jayfoad, arsenm, cdevadas and vikramRH August 21, 2024 10:09

AditiRM self-assigned this Aug 21, 2024

jayfoad reviewed Aug 21, 2024

View reviewed changes

arsenm reviewed Aug 21, 2024

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llvm/test/CodeGen/AMDGPU/phi-moveimm-subreg-input.mir Outdated Show resolved Hide resolved

Handle review comments

e5f73a0

Addition of illegal AGPR to SGPR copies and update with review changes

AditiRM requested review from jayfoad and arsenm August 27, 2024 10:04

AditiRM marked this pull request as ready for review August 27, 2024 10:07

cdevadas reviewed Aug 27, 2024

View reviewed changes

AditiRM changed the title ~~[AMDGPU] Add MachineVerifer check to detect illegal copies from VGPR to SGPR~~ [AMDGPU] Add MachineVerifer check to detect illegal copies from vector registers to SGPR Aug 28, 2024

AditiRM changed the title ~~[AMDGPU] Add MachineVerifer check to detect illegal copies from vector registers to SGPR~~ [AMDGPU] Add MachineVerifer check to detect illegal copies from vector register to SGPR Aug 28, 2024

Handle Review comments

9c89b57

introduced vector register illegal copies for both VGPR and AGPR, removed subreg-input testcase scenario, updated the testcase error checks accordingly

AditiRM requested a review from cdevadas August 28, 2024 05:02

cdevadas approved these changes Aug 28, 2024

View reviewed changes

AditiRM changed the title ~~[AMDGPU] Add MachineVerifer check to detect illegal copies from vector register to SGPR~~ [AMDGPU] Add MachineVerifier check to detect illegal copies from vector register to SGPR Aug 28, 2024

arsenm reviewed Aug 28, 2024

View reviewed changes

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp Outdated Show resolved Hide resolved

arsenm reviewed Aug 28, 2024

View reviewed changes

Merge branch 'main' into machine-verify

f23e81a

AditiRM mentioned this pull request Sep 2, 2024

[AMDGPU] Create dir for amdgpu specific machineverifier tests #106960

Merged

Handle review comments

320bc25

Removed the redundancy of isGenericOpcode check, now isCopy check is indepenent of Generic Opcodes (GISEL pipeline) & SDAG piepeline

AditiRM pushed a commit that referenced this pull request Sep 3, 2024

[AMDGPU] Create dir for amdgpu specific machineverifier tests (#106960)

d24a2fd

Move the AMDGPU target specific testcases in MachineVerifier separately into new directory. Reference : #105494 (comment)

Merge branch 'main' into machine-verify

bdef10e

Move testcase into AMDGPU directory

b503184

AditiRM force-pushed the machine-verify branch from c53b683 to b503184 Compare September 3, 2024 10:19

AditiRM added 3 commits September 6, 2024 15:40

Modify subreg testcase

e87b685

Fix trailing whitespace in SIInstrInfo.cpp

ee2acc2

Format testcase

a99440e

AditiRM requested a review from arsenm September 6, 2024 10:34

arsenm approved these changes Sep 6, 2024

View reviewed changes

AditiRM mentioned this pull request Sep 12, 2024

[AMDGPU] Precommit and Modify phi_moveimm_subreg_input testcase #108389

Merged

AditiRM mentioned this pull request Sep 18, 2024

[AMDGPU] Handle subregisters properly in generic operand legalizer #108496

Merged

Merge branch 'main' into machine-verify

36ca00d

AditiRM requested a review from cdevadas September 18, 2024 10:06

cdevadas reviewed Sep 19, 2024

View reviewed changes

Handle review changes

2626818

AditiRM merged commit 60a8b2b into llvm:main Sep 19, 2024
8 checks passed

cdevadas reviewed Sep 19, 2024

View reviewed changes

[AMDGPU] Add MachineVerifier check to detect illegal copies from vector register to SGPR #105494

[AMDGPU] Add MachineVerifier check to detect illegal copies from vector register to SGPR #105494

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AditiRM Sep 9, 2024 • edited Loading Uh oh! There was an error while loading. Please reload this page.

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