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Merged
merged 1 commit into from
Oct 27, 2025
+5 −8
Merged

Bump LLVM #9121

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2 changes: 1 addition & 1 deletion lib/Dialect/FIRRTL/Transforms/AssignOutputDirs.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -40,7 +40,7 @@ static void makeAbsolute(StringRef outputDir,
auto sep = llvm::sys::path::get_separator();
if (!moduleOutputDir.empty())
assert(moduleOutputDir.ends_with(sep));
fs::make_absolute(outputDir, moduleOutputDir);
path::make_absolute(outputDir, moduleOutputDir);
path::remove_dots(moduleOutputDir, true);
moduleOutputDir += sep;
}
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2 changes: 1 addition & 1 deletion llvm
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Submodule llvm updated 10619 files
9 changes: 3 additions & 6 deletions test/Dialect/Seq/hw-memsim.mlir
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Expand Up @@ -104,8 +104,7 @@ hw.module.generated @FIRRTLMem_1_1_1_16_10_0_1_0_0, @FIRRTLMem(in %ro_addr_0: i4
//CHECK-NEXT: %[[rwdata2:.+]] = comb.mux %[[rwrcond]], %[[rwdata]], %[[x2]]
//CHECK-NEXT: sv.assign %[[rwtmp]], %[[rwdata2:.+]]
//CHECK-NEXT: sv.always posedge %rw_clock_0 {
//CHECK-NEXT: %[[rwwcondpre:.+]] = comb.and %rw_wmode_0, %true
//CHECK-NEXT: %[[rwwcond:.+]] = comb.and %rw_en_0, %[[rwwcondpre]]
//CHECK-NEXT: %[[rwwcond:.+]] = comb.and %rw_en_0, %rw_wmode_0
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This is surprising. I assume something changed upstream with more/better/fixed running of canonicalizers?

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Good point, I think this is related llvm/llvm-project#160615. createOrFold is used in HWMemSimImpl and the PR changes createOrFold to apply folding until settled.

//CHECK-NEXT: sv.if %[[rwwcond]] {
//CHECK-NEXT: %[[rwwslot:.+]] = sv.array_index_inout %Memory[%rw_addr_0]
//CHECK-NEXT: %[[c0_i32:.+]] = hw.constant 0 : i32
Expand Down Expand Up @@ -393,8 +392,7 @@ hw.module.generated @ReadWriteWithHighReadLatency, @FIRRTLMem(in %rw_addr: i4, i

// Write port
// CHECK: sv.always
// CHECK: [[TMP:%.+]] = comb.and [[WMODE_1R]], %true
// CHECK: [[WCOND:%.+]] comb.and [[EN_1R]], [[TMP]]
// CHECK: [[WCOND:%.+]] comb.and [[EN_1R]], [[WMODE_1R]]
// CHECK: [[WPTR:%.+]] = sv.array_index_inout [[MEM]][[[ADDR_1R]]]

// COMMON-LABEL: hw.module private @ReadWriteWithHighWriteLatency
Expand Down Expand Up @@ -442,8 +440,7 @@ hw.module.generated @ReadWriteWithHighWriteLatency, @FIRRTLMem(in %rw_addr: i4,

// Write port
// CHECK: sv.always
// CHECK: [[TMP:%.+]] = comb.and [[WRITE_WMODE_3R]], %true
// CHECK: [[WCOND:%.+]] comb.and [[WRITE_EN_3R]], [[TMP]]
// CHECK: [[WCOND:%.+]] comb.and [[WRITE_EN_3R]], [[WRITE_WMODE_3R]]
// CHECK: [[WPTR:%.+]] = sv.array_index_inout [[MEM]][[[WRITE_ADDR_3R]]]

emit.fragment @Fragment {}
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