[Synth] LowerWordsToBits: Improve scalability with bit-sensitive constprop

include/circt/Dialect/Synth/SynthOps.h

@@ -38,6 +38,15 @@ struct AndInverterVariadicOpConversion
                   mlir::PatternRewriter &rewriter) const override;
 };
 
+/// This function performs a topological sort on the operations within each
+/// block of graph regions in the given operation. It uses MLIR's topological
+/// sort utility as a wrapper, ensuring that operations are ordered such that
+/// all operands are defined before their uses. The `isOperandReady` callback
+/// allows customization of when an operand is considered ready for sorting.
+LogicalResult topologicallySortGraphRegionBlocks(
+    mlir::Operation *op,
+    llvm::function_ref<bool(mlir::Value, mlir::Operation *)> isOperandReady);
+
 } // namespace synth
 } // namespace circt
 

include/circt/Dialect/Synth/Transforms/SynthPasses.td

@@ -84,6 +84,14 @@ def LowerVariadic : Pass<"synth-lower-variadic", "hw::HWModuleOp"> {
 def LowerWordToBits : Pass<"synth-lower-word-to-bits", "hw::HWModuleOp"> {
   let summary = "Lower multi-bit AndInverter to single-bit ones";
   let dependentDialects = ["comb::CombDialect"];
+  let statistics = [
+    Statistic<"numLoweredBits", "num-lowered-bits",
+              "Number of total bits lowered including constant">,
+    Statistic<"numLoweredConstants", "num-lowered-constants",
+              "Number of total constant bits lowered">,
+    Statistic<"numLoweredOps", "num-lowered-ops",
+              "Number of total operations lowered">,
+  ];
 }
 
 def PrintLongestPathAnalysis

lib/Dialect/Synth/SynthOps.cpp

@@ -10,12 +10,14 @@
 #include "circt/Dialect/HW/HWOps.h"
 #include "circt/Support/CustomDirectiveImpl.h"
 #include "circt/Support/Naming.h"
+#include "mlir/Analysis/TopologicalSortUtils.h"
 #include "mlir/IR/BuiltinAttributes.h"
 #include "mlir/IR/Matchers.h"
 #include "mlir/IR/OpDefinition.h"
 #include "mlir/IR/PatternMatch.h"
 #include "llvm/ADT/APInt.h"
 #include "llvm/Support/Casting.h"
+#include "llvm/Support/LogicalResult.h"
 
 using namespace mlir;
 using namespace circt;
@@ -301,3 +303,25 @@ LogicalResult circt::synth::AndInverterVariadicOpConversion::matchAndRewrite(
                              op, op.getOperands(), op.getInverted(), rewriter));
   return success();
 }
+
+LogicalResult circt::synth::topologicallySortGraphRegionBlocks(
+    mlir::Operation *op,
+    llvm::function_ref<bool(mlir::Value, mlir::Operation *)> isOperandReady) {
+  // Sort the operations topologically
+  auto walkResult = op->walk([&](Region *region) {
+    auto regionKindOp =
+        dyn_cast<mlir::RegionKindInterface>(region->getParentOp());
+    if (!regionKindOp ||
+        regionKindOp.hasSSADominance(region->getRegionNumber()))
+      return WalkResult::advance();
+
+    // Graph region.
+    for (auto &block : *region) {
+      if (!mlir::sortTopologically(&block, isOperandReady))
+        return WalkResult::interrupt();
+    }
+    return WalkResult::advance();
+  });
+
+  return success(!walkResult.wasInterrupted());
+}

lib/Dialect/Synth/Transforms/CutRewriter.cpp

@@ -122,30 +122,15 @@ static bool compareDelayAndArea(OptimizationStrategy strategy, double newArea,
 LogicalResult
 circt::synth::topologicallySortLogicNetwork(mlir::Operation *topOp) {
 
-  // Sort the operations topologically
-  auto walkResult = topOp->walk([&](Region *region) {
-    auto regionKindOp =
-        dyn_cast<mlir::RegionKindInterface>(region->getParentOp());
-    if (!regionKindOp ||
-        regionKindOp.hasSSADominance(region->getRegionNumber()))
-      return WalkResult::advance();
-
-    auto isOperationReady = [&](Value value, Operation *op) -> bool {
-      // Topologically sort simulatable ops and purely
-      // dataflow ops. Other operations can be scheduled.
-      return !(isSupportedLogicOp(op) ||
-               isa<comb::ExtractOp, comb::ReplicateOp, comb::ConcatOp>(op));
-    };
-
-    // Graph region.
-    for (auto &block : *region) {
-      if (!mlir::sortTopologically(&block, isOperationReady))
-        return WalkResult::interrupt();
-    }
-    return WalkResult::advance();
-  });
+  auto isOperationReady = [](Value value, Operation *op) -> bool {
+    // Topologically sort simulatable ops and purely
+    // dataflow ops. Other operations can be scheduled.
+    return !(isSupportedLogicOp(op) ||
+             isa<comb::ExtractOp, comb::ReplicateOp, comb::ConcatOp>(op));
+  };
 
-  if (walkResult.wasInterrupted())
+  auto result = topologicallySortGraphRegionBlocks(topOp, isOperationReady);
+  if (failed(result))
     return mlir::emitError(topOp->getLoc(),
                            "failed to sort operations topologically");
   return success();