Skip to content

[Verif] fix : Verif Clock I1 to !seq.clock #8907

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom
Draft
wants to merge 1 commit into
base: main
Choose a base branch
from
Draft

[Verif] fix : Verif Clock I1 to !seq.clock #8907

wants to merge 1 commit into from
+13 −15

Conversation

markram1729
Copy link
Contributor

Possible fix for #8810

  • Add Clocktype to ClockedAsser Replacing I1 for clk
  • Add MLIR test changes in test/Dialect

@uenoku uenoku changed the title fix : Verif CLock I1 to !seq.clock [Verif] fix : Verif Clock I1 to !seq.clock Aug 30, 2025
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers
No reviews
Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
1 participant
@markram1729