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[ImportVerilog] Add rvalue assignment pattern support #7428

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merged 1 commit into from
Aug 4, 2024

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fabianschuiki
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Add support for assignment patterns like '{42, 9001} in rvalue position. These are roughly SystemVerilog's equivalent of struct_create and array_create. This commit also adds an array_create op to support assignment patterns for arrays.

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LGTM!

Comment on lines +746 to +748
for (unsigned replIdx = 1; replIdx < replCount; ++replIdx)
for (unsigned elementIdx = 0; elementIdx < elementCount; ++elementIdx)
elements.push_back(elements[elementIdx]);
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nit: With the existing tests, the elementCount is always 1. I noticed that slang supports arr = '{3{'{3{'0, '1}}}};. I'm not sure whether {'0, '1} is considered two element counts. Maybe we can add this as a case.

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Excellent point! I have adjusted the tests to cover the case you're describing 😃

Add support for assignment patterns like `'{42, 9001}` in rvalue
position. These are roughly SystemVerilog's equivalent of
`struct_create` and `array_create`. This commit also adds an
`array_create` op to support assignment patterns for arrays.
@fabianschuiki fabianschuiki merged commit e95e92d into main Aug 4, 2024
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@fabianschuiki fabianschuiki deleted the fschuiki/moore-assign-patterns branch August 4, 2024 18:01
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2 participants