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[ExportVerilog] Spill LTL operands used in event control if not allowed. #6829

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merged 8 commits into from
Mar 14, 2024

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dtzSiFive
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@dtzSiFive dtzSiFive commented Mar 14, 2024

When disallowing expressions in "event control", also disallow the disable iff condition to be inlined.
Do same for the clock op's clock operand.

When disallowing expressions in "event control", also disallow
the disable iff condition to be inlined.
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@fabianschuiki fabianschuiki left a comment

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LGTM! Thanks for fixing this 😍

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@uenoku uenoku left a comment

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LGTM

Walking users is just walking uses and having the iterator
call getOwner() for you anyway, so just walk uses to make checking
the operand simpler / more efficient / direct.
@dtzSiFive dtzSiFive changed the title [ExportVerilog] Disallow disable iff cond to be inlined based on option. [ExportVerilog] Spill LTL operands used in event control if not allowed. Mar 14, 2024
@dtzSiFive dtzSiFive merged commit d6dabdc into llvm:main Mar 14, 2024
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@dtzSiFive dtzSiFive deleted the fix/disable-iff-inline-expr branch March 14, 2024 17:51
seldridge pushed a commit that referenced this pull request Mar 14, 2024
…ed. (#6829)

When disallowing expressions in "event control", also disallow
the disable iff condition to be inlined and clock op's clock condition.
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4 participants