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[FIRRTL][LowerAnnotations] Fix non-probe type compat check. #6822

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Mar 14, 2024
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2 changes: 1 addition & 1 deletion lib/Dialect/FIRRTL/Transforms/LowerAnnotations.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -858,7 +858,7 @@ LogicalResult LowerAnnotationsPass::solveWiringProblems(ApplyState &state) {
// Otherwise they must be identical or FIRRTL type-equivalent
// (connectable).
if (sourceFType != sinkFType &&
!areTypesEquivalent(sourceFType, sinkFType)) {
!areTypesEquivalent(sinkFType, sourceFType)) {
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Type equivalence is not commutative? This seems like an issue with the type equivalence check?

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LOL yeah it's not symmetric and therefore also not an equivalence relation, possibly for other reasons I'm forgetting. This is @mmaloney-sf's favorite part about it 🙃 😉 .

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To be clear this is the FIRRTL spec's notion of "type equivalence", I don't think it's bugged (not for lack of being an equivalence anway) but at a very-quick glance it doesn't mention const there presently, although it's still not symmetric (Reset can connect to UInt, can't connect UInt to Reset).

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Good point about resets which are obviously not commutative.

I think the problem here is more that the spec is presenting this as an "equivalence" when it's really "verification of connection source and destination". It's not inherently wrong that equality isn't commutative, it's just weird.

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Right, shouldn't be calling its connectivity rules (or whatever) equivalence or equality probably as that's misleading if nothing else. I haven't checked but can't help but wonder if it was originally a proper equivalence and then drifted or something. Welp.

Anyway, mind approving the PR? 👍

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I think it was before abstract reset. The spec was always written as something like "the source and destination must be equivalent types (see type equivalence section for a definition)." Notably, I don't think that "type equivalence" actually mattered except for connects. I.e., this was always that aforementioned connect verification. We should probably just roll it into the connect section.

auto diag = mlir::emitError(source.getLoc())
<< "Wiring Problem source type " << sourceType
<< " does not match sink type " << sinkType;
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29 changes: 29 additions & 0 deletions test/Dialect/FIRRTL/legacy-wiring.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -206,3 +206,32 @@ firrtl.circuit "IntWidths" attributes {
firrtl.connect %x, %invalid_ui1 : !firrtl.uint, !firrtl.uint
}
}

// -----

// Check direction of compatibility using const/non-const issue encountered (#6819).
firrtl.circuit "Issue6819" attributes {
rawAnnotations = [
{
class = "firrtl.passes.wiring.SourceAnnotation",
target = "~Issue6819|Bar>y",
pin = "xyz"
},
{
class = "firrtl.passes.wiring.SinkAnnotation",
target = "~Issue6819|Issue6819>x",
pin = "xyz"
}
]} {
firrtl.module private @Bar() {
%y = firrtl.wire interesting_name : !firrtl.const.uint<4>
}
// CHECK-LABEL: module @Issue6819
firrtl.module @Issue6819() {
// CHECK: firrtl.connect %x, %{{[^ ]*}} : !firrtl.uint, !firrtl.const.uint<4>
firrtl.instance bar interesting_name @Bar()
%x = firrtl.wire interesting_name : !firrtl.uint
%invalid_ui1 = firrtl.invalidvalue : !firrtl.uint
firrtl.connect %x, %invalid_ui1 : !firrtl.uint, !firrtl.uint
}
}
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