[ExportVerilog][PrettifyVerilog] Fix exprInEventControl

[uenoku]

This commit fixes bugs in spilling logic regarding expressions used in sensitivity list.

• PrettifyVerilog is changed to check lowering options so that CSEd expressions are not cloned into users when exprInEventControl is enabled.
• There was a duplicated logic in isExpressionUnableToInline and PrepareForEmission so the logic was unified into isExpressionUnableToInline.

Fix #4620

; with --lowering-options=exprInEventControl
  always @(posedge clock or posedge ~rst_n) begin
    if (~rst_n)
      r <= 1'h0;
    else
      r <= d;

; w/o --lowering-options=exprInEventControl
  wire _GEN = ~rst_n;
  always @(posedge clock or posedge _GEN) begin
    if (_GEN)
      r <= 1'h0;
    else
      r <= d;

[seldridge]

LGTM

[seldridge]

Great! This is way better handled by one of the pre-passes. 👍