Support sequential module; initial implement of lowering BufferOp #42
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| @@ -143,10 +149,10 @@ static std::string getSubModuleName(Operation *oldOp) { | |||
| /// circuit is pure combinational logic. If graph cycle exists, at least one | |||
| /// buffer is required to be inserted for breaking the cycle, which will be | |||
| /// supported in the next patch. | |||
| static FModuleOp createTopModuleOp(handshake::FuncOp funcOp, | |||
| static FModuleOp createTopModuleOp(handshake::FuncOp funcOp, bool hasClock, | |||
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Why bother to make this optional? I think we can just always generate this. Alternatively, there should be a list of clocks to support multi-clock designs.
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Good point. Let me try to support multiple clocks.
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| Value clock = portList[2][0]; | ||
| Value reset = portList[3][0]; | ||
| } |
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Seems like you're missing something here?
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Yes, the logic is not implemented in this patch. The buffer sub-module is an empty placeholder.
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Like I mentioned in the patch description, since the buffer here can be implemented separately as an IP, maybe that is a more convenient way.
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Support sequential logic now! Sequential sub-modules will have clock and reset signals as arguments.
Currently the only supported sequential sub-module is buffer, which is lowered from handshake::BufferOp. In this patch, the logic of buffer is not implemented and the buffer sub-module is an empty placeholder.
BTW, since some components (e.g. buffers and some handshake elastic operations) can be implemented in FIRRTL / Verilog separately as parameterized template / IP, and imported through FIRParser, do you think this is a better way for the implementation of components like buffers?