Update dialect overview diagram

docs/dialects.dot

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+Digraph G {
+  // Note: Remember to run the circt/utils/update-docs-dialects.sh script after
+  // modifying this file to regenerate the .svg and .png renders of the graph.
+  rankdir = TB
+  splines=spline;
+  node [shape=box style=filled fillcolor="white"]
+  nodesep=0.2 // horizontal compression
+  ranksep=0.5 // vertical compression
+
+  // MLIR dialects
+  subgraph cluster_mlir {
+    label = "Upstream MLIR";
+    SCF [fillcolor="lightblue"]
+    Standard [fillcolor="lightblue"]
+    Arith [fillcolor="lightblue"]
+    Affine [fillcolor="lightblue"]
+  }
+
+  // ===== Nodes =====
+
+  subgraph cluster_circt {
+    label = "CIRCT"
+    // CIRCT dialects
+    Calyx [URL="https://circt.llvm.org/docs/Dialects/Calyx/"]
+    Handshake [URL="https://circt.llvm.org/docs/Dialects/Handshake/"]
+    FIRRTL [URL="https://circt.llvm.org/docs/Dialects/FIRRTL/"]
+    LLHD [URL="https://circt.llvm.org/docs/Dialects/LLHD/"]
+    HW [URL="https://circt.llvm.org/docs/Dialects/HW/"]
+    SV [URL="https://circt.llvm.org/docs/Dialects/SV/"]
+    Comb [URL="https://circt.llvm.org/docs/Dialects/Comb/"]
+    Seq [URL="https://circt.llvm.org/docs/Dialects/Seq/"]
+    StaticLogic [URL="https://circt.llvm.org/docs/Dialects/StaticLogic/"]
+    MSFT [URL="https://circt.llvm.org/docs/Dialects/MSFT/"]
+    ESI [URL="https://circt.llvm.org/docs/Dialects/ESI/"]
+    FSM [URL="https://circt.llvm.org/docs/Dialects/FSM/"]
+
+    // Internal tools
+    ExportVerilog [fillcolor="darksalmon"]
+    FIRRTLParser [label="FIRRTL Parser" fillcolor="darksalmon"]
+    Scheduling [fillcolor="darksalmon"]
+    llhd_sim [label="LLHD Sim" fillcolor="darksalmon"]
+    PyCDE [fillcolor="darksalmon"]
+  }
+
+  // External tools
+  Moore [shape=octagon fillcolor="gold"]
+  Circilator [shape=octagon fillcolor="gold" style="dashed,filled"]
+  Calyx_native [label="Calyx Native" shape=octagon fillcolor="gold"]
+
+  // File formats
+  VCDTrace [label=".vcd" fillcolor="yellowgreen" shape=note]
+  CPPFile [label=".cpp" fillcolor="yellowgreen" shape=note]
+  SVFile [label=".sv" fillcolor="yellowgreen" shape=note]
+  CapNProto [label="Cap'n Proto" fillcolor="yellowgreen" shape=note]
+  TCL [label=".tcl" fillcolor="yellowgreen" shape=note]
+  FIRFile [label=".fir" fillcolor="yellowgreen" shape=note]
+  SVVHDL [label=".sv/.vhd" fillcolor="yellowgreen" shape=note]
+  PyFile [label=".py" fillcolor="yellowgreen" shape=note]
+
+  // ===== Connections =====
+
+  // Dialect conversions
+  SCF -> Calyx
+  Affine -> StaticLogic [style=dashed]
+  StaticLogic -> Calyx [style=dashed]
+  Standard -> Calyx
+  Arith -> Calyx
+  Standard -> Handshake
+  Arith -> Handshake
+
+  Handshake -> FIRRTL
+  Calyx -> FSM [style=dashed]
+  Seq -> SV
+  FIRRTL -> HW
+  FSM -> HW
+  ESI -> HW
+  MSFT -> HW
+  HW -> LLHD
+  FIRRTL->Comb
+  Comb -> ExportVerilog
+
+  // Tool flows
+  Scheduling -> StaticLogic [dir=both]
+  FIRFile -> FIRRTLParser
+  FIRRTLParser -> FIRRTL
+  HW -> ExportVerilog
+  SV -> ExportVerilog
+  SVVHDL -> Moore [weight=999]
+  Moore -> LLHD
+  LLHD -> Circilator [style=dashed]
+  HW -> Circilator [style=dashed]
+  Calyx -> Calyx_native
+  ExportVerilog -> SVFile
+  Circilator -> CPPFile [style=dashed]
+  LLHD -> llhd_sim
+  Comb -> llhd_sim
+  HW -> llhd_sim
+  Seq -> llhd_sim
+  llhd_sim -> VCDTrace
+  Calyx_native -> SVFile
+  ESI -> CapNProto
+  MSFT -> TCL
+  PyFile -> PyCDE
+  PyCDE -> HW
+  PyCDE -> Comb
+  PyCDE -> Seq
+  PyCDE -> LLHD
+  PyCDE -> ESI [style=dashed]
+
+  // ====== Some fake edges to coerce a good layout ======
+  // Note: Modify these if you make changes to the above diagram, and things
+  // start looking weird.
+  Standard -> Scheduling [weight=999 style=invis]
+  FIRFile -> PyFile [weight=999 style=invis]
+  Calyx -> Calyx_native [weight=999 style=invis]
+  Calyx_native -> SVVHDL [weight=999 style=invis]
+
+  // Fix the following sink nodes below the CIRCT cluster
+  llhd_sim -> SVFile [weight=999 style=invis]
+  llhd_sim -> Circilator [weight=999 style=invis]
+  llhd_sim -> TCL [weight=999 style=invis]
+  llhd_sim -> CapNProto [weight=999 style=invis]
+}