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[ESI][PyCDE] Callback service (#7153)
Call software functions from hardware.
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# ===- esitester.py - accelerator for testing ESI functionality -----------===// | ||
# | ||
# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | ||
# See https://llvm.org/LICENSE.txt for license information. | ||
# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
# | ||
# ===----------------------------------------------------------------------===// | ||
# | ||
# This accelerator is intended to eventually grow into a full ESI accelerator | ||
# test image. It will be used both to test system functionality and system | ||
# performance. The corresponding software appliciation in the ESI runtime and | ||
# the ESI cosim. Where this should live longer-term is a unclear. | ||
# | ||
# ===----------------------------------------------------------------------===// | ||
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# REQUIRES: esi-runtime, esi-cosim, rtl-sim, esitester | ||
# RUN: rm -rf %t | ||
# RUN: mkdir %t && cd %t | ||
# RUN: %PYTHON% %s %t 2>&1 | ||
# RUN: esi-cosim.py -- esitester cosim env | FileCheck %s | ||
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import pycde | ||
from pycde import AppID, Clock, Module, Reset, generator | ||
from pycde.bsp import cosim | ||
from pycde.constructs import Wire | ||
from pycde.esi import CallService | ||
from pycde.types import Bits, Channel, UInt | ||
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import sys | ||
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class PrintfExample(Module): | ||
"""Call a printf function on the host once at startup.""" | ||
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clk = Clock() | ||
rst = Reset() | ||
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@generator | ||
def construct(ports): | ||
# CHECK: PrintfExample: 7 | ||
arg_data = UInt(32)(7) | ||
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sent_signal = Wire(Bits(1), "sent_signal") | ||
sent = Bits(1)(1).reg(ports.clk, | ||
ports.rst, | ||
ce=sent_signal, | ||
rst_value=Bits(1)(0)) | ||
arg_valid = ~sent & ~ports.rst | ||
arg_chan, arg_ready = Channel(UInt(32)).wrap(arg_data, arg_valid) | ||
sent_signal.assign(arg_ready & arg_valid) | ||
CallService.call(AppID("PrintfExample"), arg_chan, Bits(0)) | ||
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class EsiTesterTop(Module): | ||
clk = Clock() | ||
rst = Reset() | ||
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@generator | ||
def construct(ports): | ||
PrintfExample(clk=ports.clk, rst=ports.rst) | ||
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if __name__ == "__main__": | ||
s = pycde.System(cosim.CosimBSP(EsiTesterTop), | ||
name="EsiTester", | ||
output_directory=sys.argv[1]) | ||
s.compile() | ||
s.package() |
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// REQUIRES: esi-cosim, esi-runtime, rtl-sim, esitester | ||
// RUN: rm -rf %t6 && mkdir %t6 && cd %t6 | ||
// RUN: circt-opt %s --esi-connect-services --esi-appid-hier=top=top --esi-build-manifest=top=top --esi-clean-metadata > %t4.mlir | ||
// RUN: circt-opt %t4.mlir --lower-esi-to-physical --lower-esi-bundles --lower-esi-ports --lower-esi-to-hw=platform=cosim --lower-seq-to-sv --lower-hwarith-to-hw --canonicalize --export-split-verilog -o %t3.mlir | ||
// RUN: cd .. | ||
// RUN: esi-cosim.py --source %t6 --top top -- esitester cosim env | FileCheck %s | ||
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hw.module @EsiTesterTop(in %clk : !seq.clock, in %rst : i1) { | ||
hw.instance "PrintfExample" sym @PrintfExample @PrintfExample(clk: %clk: !seq.clock, rst: %rst: i1) -> () | ||
} | ||
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// CHECK: PrintfExample: 7 | ||
hw.module @PrintfExample(in %clk : !seq.clock, in %rst : i1) { | ||
%0 = hwarith.constant 7 : ui32 | ||
%true = hw.constant true | ||
%false = hw.constant false | ||
%1 = seq.compreg.ce %true, %clk, %5 reset %rst, %false : i1 | ||
%true_0 = hw.constant true | ||
%2 = comb.xor bin %1, %true_0 : i1 | ||
%true_1 = hw.constant true | ||
%3 = comb.xor bin %rst, %true_1 {sv.namehint = "inv_rst"} : i1 | ||
%4 = comb.and bin %2, %3 : i1 | ||
%chanOutput, %ready = esi.wrap.vr %0, %4 : ui32 | ||
%5 = comb.and bin %ready, %4 {sv.namehint = "sent_signal"} : i1 | ||
%6 = esi.service.req <@_CallService::@call>(#esi.appid<"PrintfExample">) : !esi.bundle<[!esi.channel<ui32> from "arg", !esi.channel<i0> to "result"]> | ||
%result = esi.bundle.unpack %chanOutput from %6 : !esi.bundle<[!esi.channel<ui32> from "arg", !esi.channel<i0> to "result"]> | ||
} | ||
esi.service.std.call @_CallService |
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