Guide for UART Modules

Overview

This repository contains implementations of both UART Transmitter (uart_tx) and UART Receiver (uart_rx) modules, designed in SystemVerilog. These modules employ FIFO buffers and finite state machines (FSM) to manage serial data transmission and reception efficiently.

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Features

UART Transmitter (uart_tx)

• Configurable baud rate for flexible communication speeds.
• FIFO buffer to handle data storage and manage flow control.
• State machine for efficient data processing.
• Handles start, data, and stop bits as per UART protocol.

UART Receiver (uart_rx)

• Configurable baud rate for flexible communication speeds.
• FIFO buffer to handle received data and manage flow control.
• State machine for synchronized bit sampling and data reception.
• Detects start bits using edge detection.

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Directory Structure

.
├── rtl
│   ├── uart_tx.sv         # UART transmitter implementation
│   ├── uart_rx.sv         # UART receiver implementation
│   ├── fifo.sv            # FIFO buffer implementation
├── tb
│   ├── tb_tx.sv           # Testbench for UART transmitter
│   ├── tb_rx.sv           # Testbench for UART receiver
│   ├── tb_top.sv          # Testbench for top-level module
├── Makefile               # For compiling and simulating with ModelSim
├── xdc
│   ├── Basys3.xdc         # Constraints file for FPGA testing

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Usage

Simulation

To simulate the design, use the provided Makefile. Ensure that ModelSim or QuestaSim is installed on your system.

1. Compile the design and testbench:

   make compile
   

2. Run the simulation:

   make simulate
   

3. Clean up generated files:

   make clean
   

FPGA Testing

To deploy the design on a Basys3 FPGA board:

1. Prepare the Design:

   • Add the provided Basys3.xdc file to your Vivado project for pin mapping.
   • Include the top_module.sv as the top-level module.

2. Synthesize and Implement:

   • Synthesize the design and resolve any timing violations.
   • Generate a bitstream file for programming the FPGA.

3. Program the FPGA:

   • Connect the Basys3 board to your PC.
   • Use Vivado or another FPGA tool to load the bitstream file onto the board.

4. Test the Design:

   • Inputs: Use the onboard switches to provide button_data and control signals (tx_en_i, tx_we_i, rx_en_i, rx_re_i).
   • Outputs: Verify the received data on the LEDs and monitor the FIFO status signals (tx_full, tx_empty, rx_full, rx_empty). You can test both TX and RX using fpga environment. Give input usign push buttons for tx and read data from rx using leds.

Files

• uart_tx.sv: The main UART transmitter module.
• uart_rx.sv: The main UART receiver module.
• fifo.sv: A parameterized FIFO implementation for buffering data.
• tb_tx.sv: A testbench for verifying the UART transmitter.
• tb_rx.sv: A testbench for verifying the UART receiver.
• tb_top.sv: A testbench for verifying the top-level integration.
• Basys3.xdc: Constraints file for FPGA pin assignments.

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How It Works

UART Transmitter (uart_tx)

1. FIFO Buffer:

   • Stores data to be transmitted.
   • Handles flow control with full_o and empty_o signals.

2. Finite State Machine (FSM):

   • IDLE: Waits for data in the FIFO.
   • LOAD: Loads data from FIFO into the shift register.
   • SENDING: Transmits start, data, and stop bits serially.

3. Baud Clock:

   • Derived from baud_div_i to control the transmission rate.

UART Receiver (uart_rx)

1. FIFO Buffer:

   • Stores received data.
   • Handles flow control with full_o and empty_o signals.

2. Finite State Machine (FSM):

   • IDLE: Waits for a falling edge on rx_bit_i to detect the start bit.
   • SAMPLING: Samples 8 data bits sequentially using the baud clock and writes them to the FIFO buffer.

3. Baud Clock:

   • Derived from baud_div_i to control the sampling rate.

4. Edge Detection:

   • Detects the start bit using rx_bit_i and synchronizes the sampling process.

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Notes

• Ensure that the baud divisor (baud_div_i) is correctly configured to match the baud rate of the communication system.
• The FIFO depth is parameterized and can be adjusted as needed for different applications.
• The current implementation of uart_rx does not explicitly check the stop bit, which may result in framing errors if the incoming frame is malformed.

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Conclusion

This repository provides robust implementations of UART transmitter and receiver modules, along with testbenches for thorough validation. For FPGA deployment, use the provided Basys3.xdc file and follow the testing instructions. For further details or issues, please refer to the module-specific guides or contact the repository owner.