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Commits on Jul 31, 2020

• Add Additional Support for Intel

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  jdtarang

  committed
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• Update Makefile

  jdtarang

  committed
  b5bce8b

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• Fix bug in makefile

  jdtarang

  committed
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Commits on Jul 30, 2020

• Add intel make requirements and files

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  jdtarang

  committed
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• Altera S 10 GX Dev board bit stream generation.

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  jdtarang

  committed
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Commits on Jul 18, 2020

• Add Project

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  jdtarang

  committed
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• Update

  jdtarang

  committed
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• Update

  jdtarang

  committed
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Commits on Jul 17, 2020

• Update builds

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  jdtarang

  committed
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Commits on Jul 16, 2020

• Update to makefile system

  jdtarang

  committed
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Commits on Feb 13, 2020

• Add sgx execution updates.

  jdtarang

  committed
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• Add Intel SGX Scala

  jtarango

  committed
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Commits on Feb 7, 2020

• Add Intel support baseline.

  jtarango

  committed
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Commits on Oct 15, 2018

• SPI speedup related FPGA changes

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  mhtwn

  authored
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Commits on Oct 14, 2018

• mbus: switch to multi-bank API (#44)

  terpstra

  authored
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Commits on Oct 1, 2018

• Xilinx: Add KEEPER primitive (#42)

  mwachs5

  authored
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Commits on Aug 27, 2018

• VC707Shell: default to 1GB of RAM (what the board ships with) (#40)

  terpstra

  authored
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Commits on Aug 24, 2018

• IO Overlays: use AttachParams (#39)

  hcook

  authored
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Commits on Aug 17, 2018

• Merge pull request #38 from sifive/FE-1155-e34-arty

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  RajeshVaradharajan

  authored
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Commits on Aug 16, 2018

• Renamed arty-a7-100 to arty_a7_100. BOARD & FPGATEST_BOARD variables are inconsistant

  RajeshVaradharajan

  committed
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Commits on Aug 14, 2018

• Merge pull request #37 from sifive/FE-1155-e34-arty

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  RajeshVaradharajan

  authored
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Commits on Aug 13, 2018

• Added the arty-a7-100 board to the namespace

  RajeshVaradharajan

  committed
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• Added arty-a7-100 board

  RajeshVaradharajan

  committed
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Commits on Aug 10, 2018

• vcu118: make it possible to instantiate two PCIe interfaces at once (#36)

  terpstra

  authored
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• Merge pull request #35 from sifive/vcu118-pcie

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  terpstra

  authored
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Commits on Aug 9, 2018

• xilinx: factor out pllReset better

  terpstra

  committed
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• VCU118: add second PCIe root complex

  terpstra

  committed
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• VCU118: enable gen3 x4 with full DMA address range

  terpstra

  committed
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• xdma: use MSI decode mode

  terpstra

  committed
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• Revert "VCU118: add a PCIe deglitch hack"

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  terpstra

  committed
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• VCU118: add a PCIe deglitch hack

  terpstra

  committed
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• xdma: make parameterizable

  terpstra

  committed
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• VCU118: re-indent overlays

  terpstra

  committed
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• xilinx: ensure chiplink_b2c_rst is an IOB register

  terpstra

  committed
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• VCU118: add open-drain support for ereset_n

  terpstra

  committed
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