Add Additional Support for Intel

Intel Cyclone IV board

Author: jdtarang

intel/sgx-dev/basefiles/Makefile

@@ -151,13 +151,13 @@ VRC_FILES=../../rocket-chip/src/main/resources/vsrc/plusarg_reader.v \
 ###############################################################################
 all: clean copybase copyfiles
 	$(info DEBUG INFO)
-	quartus_sh  --flow compile $(PRJ_TOP_NAME).qpf  2>&1 | tee log.txt
-	quartus_sh  -t $(QTCL_FILE) --flow compile $(PRJ_TOP_NAME)  2>>&1 | tee log.txt
-	quartus_syn -t $(QTCL_FILE) $(PRJ_TOP_NAME) 2>>&1 | tee log.txt
-	quartus_fit -t $(QTCL_FILE) $(PRJ_TOP_NAME) 2>>&1 | tee log.txt
-	quartus_asm -t $(QTCL_FILE) $(PRJ_TOP_NAME)	2>>&1 | tee log.txt
-	quartus_sta -t $(QTCL_FILE) $(PRJ_TOP_NAME) 2>>&1 | tee log.txt
-	quartus_eda -t $(QTCL_FILE) $(PRJ_TOP_NAME) --simulation --tool=modelsim --format=verilog 2>>&1 | tee log.txt
+	quartus_sh  --flow compile $(PRJ_TOP_NAME).qpf
+	quartus_sh  -t $(QTCL_FILE) --flow compile $(PRJ_TOP_NAME)
+	quartus_syn -t $(QTCL_FILE) $(PRJ_TOP_NAME)
+	quartus_fit -t $(QTCL_FILE) $(PRJ_TOP_NAME)
+	quartus_asm -t $(QTCL_FILE) $(PRJ_TOP_NAME)
+	quartus_sta -t $(QTCL_FILE) $(PRJ_TOP_NAME)
+	quartus_eda -t $(QTCL_FILE) $(PRJ_TOP_NAME) --simulation --tool=modelsim --format=verilog
 .PHONY: all
 
 # Copy base files
@@ -178,4 +178,4 @@ clean:
 # Create a tar ball for project
 turnin:
 	$(TR) -czvf $(PRJ_TOP_NAME) *
-.PHONY: turnin
+.PHONY: turnin

intel/zeowaa-e115/DC-DC-POWER.pdf

@@ -0,0 +1,82 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2020  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 176 184)
+	(text "IOBUF" (rect 69 -1 97 11)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 168 20 180)(font "Arial" ))
+	(port
+		(pt 0 72)
+		(input)
+		(text "datain" (rect 0 0 22 12)(font "Arial" (font_size 8)))
+		(text "datain" (rect 4 61 40 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 48 72)(line_width 1))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "oe" (rect 0 0 9 12)(font "Arial" (font_size 8)))
+		(text "oe" (rect 4 101 16 112)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 48 112)(line_width 1))
+	)
+	(port
+		(pt 176 72)
+		(output)
+		(text "dataout" (rect 0 0 28 12)(font "Arial" (font_size 8)))
+		(text "dataout" (rect 138 61 180 72)(font "Arial" (font_size 8)))
+		(line (pt 176 72)(pt 128 72)(line_width 1))
+	)
+	(port
+		(pt 0 152)
+		(bidir)
+		(text "padio" (rect 0 0 20 12)(font "Arial" (font_size 8)))
+		(text "padio" (rect 4 141 34 152)(font "Arial" (font_size 8)))
+		(line (pt 0 152)(pt 48 152)(line_width 1))
+	)
+	(drawing
+		(text "dout" (rect 129 43 282 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "export" (rect 98 67 232 144)(font "Arial" (color 0 0 0)))
+		(text "din" (rect 32 43 82 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "export" (rect 53 67 142 144)(font "Arial" (color 0 0 0)))
+		(text "oe" (rect 35 83 82 179)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "export" (rect 53 107 142 224)(font "Arial" (color 0 0 0)))
+		(text "pad_io" (rect 10 123 56 259)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "export" (rect 53 147 142 304)(font "Arial" (color 0 0 0)))
+		(text " IOBUF " (rect 144 168 330 346)(font "Arial" ))
+		(line (pt 48 32)(pt 128 32)(line_width 1))
+		(line (pt 128 32)(pt 128 168)(line_width 1))
+		(line (pt 48 168)(pt 128 168)(line_width 1))
+		(line (pt 48 32)(pt 48 168)(line_width 1))
+		(line (pt 127 52)(pt 127 76)(line_width 1))
+		(line (pt 126 52)(pt 126 76)(line_width 1))
+		(line (pt 49 52)(pt 49 76)(line_width 1))
+		(line (pt 50 52)(pt 50 76)(line_width 1))
+		(line (pt 49 92)(pt 49 116)(line_width 1))
+		(line (pt 50 92)(pt 50 116)(line_width 1))
+		(line (pt 49 132)(pt 49 156)(line_width 1))
+		(line (pt 50 132)(pt 50 156)(line_width 1))
+		(line (pt 0 0)(pt 176 0)(line_width 1))
+		(line (pt 176 0)(pt 176 184)(line_width 1))
+		(line (pt 0 184)(pt 176 184)(line_width 1))
+		(line (pt 0 0)(pt 0 184)(line_width 1))
+	)
+)

intel/zeowaa-e115/E115-DDR2-SODIMM.pdf

@@ -0,0 +1,9 @@
+	component IOBUF is
+		port (
+			dataout : out   std_logic_vector(0 downto 0);                    -- export
+			datain  : in    std_logic_vector(0 downto 0) := (others => 'X'); -- export
+			oe      : in    std_logic_vector(0 downto 0) := (others => 'X'); -- export
+			padio   : inout std_logic_vector(0 downto 0) := (others => 'X')  -- export
+		);
+	end component IOBUF;
+

intel/zeowaa-e115/E115-FPGA.pdf

@@ -0,0 +1,20 @@
+# system info IOBUF on 2020.07.29.10:13:24
+system_info:
+name,value
+DEVICE,1SG280LU2F50E2VG
+DEVICE_FAMILY,Stratix 10
+GENERATION_ID,0
+#
+#
+# Files generated for IOBUF on 2020.07.29.10:13:24
+files:
+filepath,kind,attributes,module,is_top
+sim/IOBUF.v,VERILOG,CONTAINS_INLINE_CONFIGURATION,IOBUF,true
+altera_gpio_1930/sim/IOBUF_altera_gpio_1930_alkbnhy.v,VERILOG,CONTAINS_INLINE_CONFIGURATION,IOBUF_altera_gpio_1930_alkbnhy,false
+altera_gpio_core14_191/sim/altera_gpio.sv,SYSTEM_VERILOG,,altera_gpio,false
+#
+# Map from instance-path to kind of module
+instances:
+instancePath,module
+IOBUF.gpio_0,IOBUF_altera_gpio_1930_alkbnhy
+IOBUF.gpio_0.core,altera_gpio