Skip to content

Commit 5e33d4b

Browse files
committed
VCU118: add open-drain support for ereset_n
1 parent 48a77ef commit 5e33d4b

File tree

1 file changed

+9
-2
lines changed

1 file changed

+9
-2
lines changed

src/main/scala/shell/xilinx/VCU118NewShell.scala

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -77,13 +77,20 @@ class ChipLinkVCU118Overlay(val shell: VCU118Shell, val name: String, params: Ch
7777
extends ChipLinkXilinxOverlay(params, rxPhase= -120, txPhase= -90, rxMargin=0.6, txMargin=0.5)
7878
{
7979
val ereset_n = shell { InModuleBody {
80-
val ereset_n = IO(Input(Bool()))
80+
val ereset_n = IO(Analog())
8181
ereset_n.suggestName("ereset_n")
8282
shell.xdc.addPackagePin(ereset_n, "BC8")
8383
shell.xdc.addIOStandard(ereset_n, "LVCMOS18")
8484
shell.xdc.addTermination(ereset_n, "NONE")
8585
shell.xdc.addPullup(ereset_n)
86-
ereset_n
86+
87+
val iobuf = Module(new IOBUF)
88+
iobuf.suggestName("chiplink_ereset_iobuf")
89+
attach(ereset_n, iobuf.io.IO)
90+
iobuf.io.T := true.B // !oe
91+
iobuf.io.I := false.B
92+
93+
iobuf.io.O
8794
} }
8895

8996
shell { InModuleBody {

0 commit comments

Comments
 (0)