Hardware Hierarchical Dynamic Structures

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Xilinx QDMA IP Drivers

Flexible Intermediate Representation for RTL

Rust wrapper around KaMinPar which is a shared-memory parallel tool to heuristically solve the graph partitioning problem

an educational compiler intermediate representation

Shared-Memory and Distributed-Memory Parallel Graph Partitioning

Rocket Chip Generator

Intermediate Language (IL) for Hardware Accelerator Generators