GitHub - joonho3020/chipyard-compiler-dev: An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Hacks / Commands

To generate FireSim testharness CHIRRTL file, run:

cd  sims/vcs
make launch-sbt
runMain firechip.chip.Generator --target-dir /scratch/joonho.whangbo/coding/chipyard-fame5/sims/vcs/generated-src/firechip.chip.FireSim.FireSimRocketConfig --name firechip.chip.FireSim.FireSimRocketConfig --top-module firechip.chip.FireSim --legacy-configs firechip.chip:FireSimRocketConfig

Name		Name	Last commit message	Last commit date
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.githooks		.githooks
.github		.github
.java_tmp		.java_tmp
conda-reqs		conda-reqs
dockerfiles		dockerfiles
docs		docs
fpga		fpga
generators		generators
project		project
scripts		scripts
sims		sims
software		software
tests		tests
toolchains		toolchains
tools		tools
vlsi		vlsi
.ciignore		.ciignore
.ctags		.ctags
.ctagsignore		.ctagsignore
.gitattributes		.gitattributes
.gitignore		.gitignore
.gitmodules		.gitmodules
.mergify.yml		.mergify.yml
.readthedocs.yml		.readthedocs.yml
CHANGELOG.md		CHANGELOG.md
CONTRIBUTING.md		CONTRIBUTING.md
LICENSE		LICENSE
LICENSE.SiFive		LICENSE.SiFive
README.md		README.md
build-setup.sh		build-setup.sh
build.sbt		build.sbt
common.mk		common.mk
variables.mk		variables.mk

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