Equivalence checking with Yosys

Xiaomi Home Integration for Home Assistant

Collection for submission (Hardware Model Checking Benchmark)

Separation Logic Proofs in Lean

SystemVerilog compiler and language services

picolibc - a C library designed for embedded 32- and 64- bit systems.

4 stage, in-order, compute RISC-V core based on the CV32E40P

RISC-V Verification Interface

DRAMSys a SystemC TLM-2.0 based DRAM simulator.

Tor Browser automation with Selenium.

爬取secwiki和xuanwu.github.io/sec.today,分析安全信息站点、安全趋势、提取安全工作者账号(twitter,weixin,github等)

A browser automation framework and ecosystem.

Sail architecture definition language with RGen enhancements

Clone of the mercurial repository http://zbar.hg.sourceforge.net:8000/hgroot/zbar/zbar

A Python library used to transfer files with QR codes. Input a file, get QR code images. Print, email, or otherwise share your codes. Re-input these QR codes, get your original file back.

TXQR (Animated QR data transfer) demo reader app for iOS

Transfer data via animated QR codes

Repo associated with benchmarks for our multi-chiplet GPU gem5 support for CPElide at MICRO '24

SystemVerilog frontend for Yosys

Extracting high level semantic information from binary code

Coq is a formal proof management system. It provides a formal language to write mathematical definitions, executable algorithms and theorems together with an environment for semi-interactive develo…

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM, 8-bit AVR and 32-bit RISC-V architectures.

SystemVerilog language server

Hardware abstraction library