jimmysitu
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msfinance Public
msfinance offers Pythonic way to download market data from morningstar.com
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spring23 Public
Forked from mit-frap/spring23Problem Sets for MIT 6.512 Formal Reasoning About Programs, Spring 2023
Coq UpdatedSep 28, 2024 -
jimmysitu.github.io Public
JM's website on github
Ruby GNU General Public License v3.0 UpdatedJul 20, 2024 -
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jmACL2 Public
JM's ACL2 playground
Common Lisp BSD 3-Clause "New" or "Revised" License UpdatedAug 9, 2023 -
nZDC-Compiler Public
Forked from MPSLab-ASU/nZDC-CompilerA LLVM-3.7 compiler with nZDC error detection transfromation
C++ UpdatedJul 17, 2023 -
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gem5 Public
Jimmy's gem5, forked from
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core-v-verif Public
Forked from openhwgroup/core-v-verifFunctional verification project for the CORE-V family of RISC-V cores.
Assembly Other UpdatedSep 6, 2022 -
verilog2smt Public
Example to transform verilog to smtlib2
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waveform-render-vscode Public
Forked from bmpenuelas/waveform-render-vscodeRender waveforms inside VSCode with WaveDrom
TypeScript UpdatedJan 29, 2022 -
pyParallelTest Public
Just a python3 parallel example
Python Apache License 2.0 UpdatedJan 17, 2022 -
GeST Public
Forked from toolsForUarch/GeSTGeST (Generating Stress-Tests) is a Genetic Algorithm framework for automatic hardware stress-test generation. Related scientific publication https://ieeexplore.ieee.org/document/8695639
Python UpdatedDec 29, 2021 -
More_Equal_Animals_Chinese_Edition Public
Forked from shinjiikarieos/More_Equal_Animals_Chinese_Edition《更平等的动物》中文版
JavaScript UpdatedDec 11, 2021 -
gem5-bench Public
A wrapper for simulation with gem5
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api-v1-client-python Public
Forked from dfkthf125/api-v1-client-pythonBlockchain Bitcoin Developer APIs - Python
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verilog-axi Public
Forked from alexforencich/verilog-axiVerilog AXI components for FPGA implementation
Verilog MIT License UpdatedJun 3, 2021 -
verilog-axi-formal Public
Formal verification for alexforencich/verilog-axi using SymbiYosys
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stx_cookbook Public
Forked from thomasrussellmurphy/stx_cookbookAltera Advanced Synthesis Cookbook 11.0
Verilog UpdatedMay 21, 2021 -
oh Public
Forked from aolofsson/ohSilicon proven Verilog library for IC and FPGA designers
Verilog MIT License UpdatedApr 26, 2021 -
FormalCourseExercise Public
Exercise of Formal Verification Courseware
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veriformal Public
Forked from wilstef/veriformalThis repository contains source code of VeriFormal simulator and translator.
UpdatedApr 14, 2021 -
vhdlformal Public
Forked from wilstef/vhdlformalThis repository stores the source code of a domain-specific language: a formalized version of VHDL embedded in Isabelle/HOL.
Isabelle BSD 2-Clause "Simplified" License UpdatedApr 7, 2021 -
jmCool Public
Jimmy's Cool Compiler, for https://lagunita.stanford.edu/courses/Engineering/Compilers/Fall2014/info
Java UpdatedFeb 18, 2021 -
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likwid Public
Forked from RRZE-HPC/likwidPerformance monitoring and benchmarking suite
C GNU General Public License v3.0 UpdatedJan 24, 2021 -
ariane Public
Forked from openhwgroup/cva6Ariane is a 6-stage RISC-V CPU capable of booting Linux
SystemVerilog Other UpdatedDec 13, 2020 -
verilog-sim-benchmarks Public
Verilog Simulator Benchmarks, a fork from verilator website