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ZCU102 C2C design: Update AXI BRAM controller address width following…
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… rebase. See #133
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tswilliams committed Nov 7, 2019
1 parent a7cfb31 commit 8718d09
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Showing 6 changed files with 28 additions and 20 deletions.
Original file line number Diff line number Diff line change
@@ -0,0 +1,2 @@

set_property -dict [list CONFIG.mem_depth {2048}] [get_ips axi_bram_ctrl_0]
1 change: 1 addition & 0 deletions boards/zcu102/c2c_loopback/synth/firmware/cfg/top.dep
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Expand Up @@ -24,6 +24,7 @@
#-------------------------------------------------------------------------------

setup settings.tcl
setup -f bram_ctrl_addr_width.tcl
setup -f add_block_designs.tcl
include zu9.dep

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Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,7 @@ architecture rtl of zynq_infra_full is
signal rst_ipb : std_logic;
signal rst_ipb_ctrl : std_logic;

signal axi_ms : axi4mm_ms(araddr(15 downto 0), awaddr(15 downto 0), wdata(63 downto 0));
signal axi_ms : axi4mm_ms(araddr(63 downto 0), awaddr(63 downto 0), wdata(63 downto 0));
signal axi_sm : axi4mm_sm(rdata(63 downto 0));

signal ipb_pkt_done : std_logic;
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24 changes: 13 additions & 11 deletions boards/zcu102/c2c_loopback/synth/firmware/hdl/c2c_m_ipb_wrapper.vhd
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Expand Up @@ -24,7 +24,7 @@ entity z_ipb_full_wrapper is
ipb_periph_rst_o : out std_logic;

ipb_irq_i : in std_logic;
ipb_axi_ms : out axi4mm_ms(araddr(15 downto 0), awaddr(15 downto 0), wdata(63 downto 0));
ipb_axi_ms : out axi4mm_ms(araddr(63 downto 0), awaddr(63 downto 0), wdata(63 downto 0));
ipb_axi_sm : in axi4mm_sm(rdata(63 downto 0))
);
end z_ipb_full_wrapper;
Expand All @@ -50,7 +50,7 @@ c2c_m_ipb_inst: entity work.c2c_m_ipb
ipb_axi_rlast => ipb_axi_sm.rlast,
ipb_axi_rvalid => ipb_axi_sm.rvalid,
-- ipb_axi_awid => axi_ms.awid,
ipb_axi_awaddr(15 downto 0) => ipb_axi_ms.awaddr, ipb_axi_awaddr(31 downto 16) => open,
ipb_axi_awaddr(15 downto 0) => ipb_axi_ms.awaddr(15 downto 0), ipb_axi_awaddr(31 downto 16) => open,
ipb_axi_awlen => ipb_axi_ms.awlen,
ipb_axi_awsize => ipb_axi_ms.awsize,
ipb_axi_awburst => ipb_axi_ms.awburst,
Expand All @@ -64,7 +64,7 @@ c2c_m_ipb_inst: entity work.c2c_m_ipb
ipb_axi_wvalid => ipb_axi_ms.wvalid,
ipb_axi_bready => ipb_axi_ms.bready,
-- ipb_axi_arid => ipb_axi_ms.arid,
ipb_axi_araddr(15 downto 0) => ipb_axi_ms.araddr, ipb_axi_araddr(31 downto 16) => open,
ipb_axi_araddr(15 downto 0) => ipb_axi_ms.araddr(15 downto 0), ipb_axi_araddr(31 downto 16) => open,
ipb_axi_arlen => ipb_axi_ms.arlen,
ipb_axi_arsize => ipb_axi_ms.arsize,
ipb_axi_arburst => ipb_axi_ms.arburst,
Expand Down Expand Up @@ -92,15 +92,17 @@ c2c_m_ipb_inst: entity work.c2c_m_ipb
gt_i_rxn(0) => gt_rxn,
gt_i_rxp(0) => gt_rxp,
gt_o_txn(0) => gt_txn,
gt_o_txp(0) => gt_txp
gt_o_txp(0) => gt_txp

);

ipb_axi_ms.aclk <= aclk;
ipb_axi_ms.aresetn <= aresetn;

aclk_o <= aclk;
aresetn_o <= aresetn;


ipb_axi_ms.aclk <= aclk;
ipb_axi_ms.aresetn <= aresetn;

aclk_o <= aclk;
aresetn_o <= aresetn;

ipb_axi_ms.awaddr(63 downto 16) <= (others => '0');
ipb_axi_ms.araddr(63 downto 16) <= (others => '0');

end STRUCTURE;
Original file line number Diff line number Diff line change
Expand Up @@ -41,7 +41,7 @@ architecture rtl of c2c_s_infra is
signal rst_ipb : std_logic;
signal rst_ipb_ctrl : std_logic;

signal axi_ms : axi4mm_ms(araddr(15 downto 0), awaddr(15 downto 0), wdata(63 downto 0));
signal axi_ms : axi4mm_ms(araddr(63 downto 0), awaddr(63 downto 0), wdata(63 downto 0));
signal axi_sm : axi4mm_sm(rdata(63 downto 0));

signal ipb_pkt_done : std_logic;
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Expand Up @@ -22,7 +22,7 @@ entity c2c_s_ipb_wrapper is
ipb_periph_rst_o : out std_logic;

ipb_irq_i : in std_logic;
ipb_axi_ms : out axi4mm_ms(araddr(15 downto 0), awaddr(15 downto 0), wdata(63 downto 0));
ipb_axi_ms : out axi4mm_ms(araddr(63 downto 0), awaddr(63 downto 0), wdata(63 downto 0));
ipb_axi_sm : in axi4mm_sm(rdata(63 downto 0))
);
end c2c_s_ipb_wrapper;
Expand All @@ -43,7 +43,7 @@ c2c_s_ipb_inst: entity work.c2c_s_ipb
ipb_axi_rlast(0) => ipb_axi_sm.rlast,
ipb_axi_rvalid(0) => ipb_axi_sm.rvalid,
-- ipb_axi_awid => ipb_axi_ms.awid,
ipb_axi_awaddr(15 downto 0) => ipb_axi_ms.awaddr, ipb_axi_awaddr(31 downto 16) => open,
ipb_axi_awaddr(15 downto 0) => ipb_axi_ms.awaddr(15 downto 0), ipb_axi_awaddr(31 downto 16) => open,
ipb_axi_awlen => ipb_axi_ms.awlen,
ipb_axi_awsize => ipb_axi_ms.awsize,
ipb_axi_awburst => ipb_axi_ms.awburst,
Expand All @@ -57,7 +57,7 @@ c2c_s_ipb_inst: entity work.c2c_s_ipb
ipb_axi_wvalid(0) => ipb_axi_ms.wvalid,
ipb_axi_bready(0) => ipb_axi_ms.bready,
-- ipb_axi_arid => ipb_axi_ms.arid,
ipb_axi_araddr(15 downto 0) => ipb_axi_ms.araddr, ipb_axi_araddr(31 downto 16) => open,
ipb_axi_araddr(15 downto 0) => ipb_axi_ms.araddr(15 downto 0), ipb_axi_araddr(31 downto 16) => open,
ipb_axi_arlen => ipb_axi_ms.arlen,
ipb_axi_arsize => ipb_axi_ms.arsize,
ipb_axi_arburst => ipb_axi_ms.arburst,
Expand All @@ -71,8 +71,8 @@ c2c_s_ipb_inst: entity work.c2c_s_ipb
-- axirstn_o(0) => ipb_axi_ms.aresetn,
aclk => aclk,
aresetn => aresetn,
c2c_stat_o => c2c_stat_o,
gtx_stat_o => gtx_stat_o,
c2c_stat_o => c2c_stat_o,
gtx_stat_o => gtx_stat_o,

ipb_clk_o => ipb_clk_o,
ipb_ic_rst_o(0) => ipb_ic_rst_o,
Expand All @@ -83,11 +83,14 @@ c2c_s_ipb_inst: entity work.c2c_s_ipb
gt_i_rxn(0) => gt_rxn,
gt_i_rxp(0) => gt_rxp,
gt_o_txn(0) => gt_txn,
gt_o_txp(0) => gt_txp
gt_o_txp(0) => gt_txp

);

ipb_axi_ms.aclk <= aclk;
ipb_axi_ms.aresetn <= aresetn;


ipb_axi_ms.awaddr(63 downto 16) <= (others => '0');
ipb_axi_ms.araddr(63 downto 16) <= (others => '0');

end STRUCTURE;

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