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Merged
merged 30 commits into from
Dec 22, 2022
Merged

Fixes: 204 #220

merged 30 commits into from
Dec 22, 2022

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akshay-wankhede
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Description & Motivation

  • Fixed: slice on a 1 bit signal should generate $x into SystemVerilog, instead of a $x[0], for single bit signals
  • Fixed: test/config_test.dart: ROHD version in wavedumper test fails on Windows, since delete temporary directory is called before the simulator run returns.
  • Fixed: IndexGate and BusSubset to generate $x into SystemVerilog, instead of $x[0] for single bit signals
  • Updated: doc comments

Related Issue(s)

Fixes: 204

Testing

  • Added: additional tests on 1 bit signals using slice, IndexGate and BusSubset

Backwards-compatibility

Is this a breaking change that will not be backwards-compatible? If yes, how so?
No.

Documentation

Does the change require any updates to documentation? If so, where? Are they included?

Yes.

@akshay-wankhede
* Added IndexGate and tests to fix issue#153
84b36e4
@akshay-wankhede
Merge branch 'intel:main' into main
d27233c
@akshay-wankhede
* Fixed: throw exception when input is neither int nor Logic
f56281e
@akshay-wankhede
* Fixed: comments, input names, made input signals private
e3d2495
@akshay-wankhede
* Fixed: index Logic by int/Logic tests
bae42e8
@akshay-wankhede
Merge branch 'main' into main
e0ddcc2
@akshay-wankhede
* Updated: doc comments
8fab660
@akshay-wankhede
* Fixed: formatting
c70ad07
@akshay-wankhede
*FIXED: lint
2b860c0
@akshay-wankhede
Merge branch 'main' into main
406af22
@akshay-wankhede
* Fixed: formatting
0696e81
@akshay-wankhede
* Fixed: cascade methods
3932d25
@akshay-wankhede
* Fixed: operator[] return slice when input is an int
34a1122
@akshay-wankhede
* Fixed: lint
d09205a
@akshay-wankhede
* Fixed: doc comment
3f04dfe
@akshay-wankhede
* Fixed: doc comments
e6b853b
@akshay-wankhede
Merge branch 'main' of https://github.com/intel/rohd
39c05f3
@akshay-wankhede
Merge branch 'main' of https://github.com/intel/rohd
dd2e521
@akshay-wankhede
* Added: single bit indexing tests
1d62e76
@akshay-wankhede
* Fixed: test fails to delete temp dir before the simulator run returns
147bed0
@akshay-wankhede
* Fixed: return $x instead of $x[0], in case the signal widht is 1; i…
3c81f57 
…gnoring indexes
@akshay-wankhede
* Fixed: return $x instead of $x[0], in case the signal widht is 1; i…
a24ab5b 
…gnoring indexes
mkorbel1
mkorbel1 requested changes Dec 7, 2022
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mkorbel1
mkorbel1 requested changes Dec 9, 2022
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A couple little doc changes, but other than that looks great!

mkorbel1
mkorbel1 requested changes Dec 19, 2022
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mkorbel1
mkorbel1 approved these changes Dec 20, 2022
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Awesome work!

@mkorbel1 mkorbel1 merged commit cb9014d into intel:main Dec 22, 2022
quekyj pushed a commit to quekyj/rohd that referenced this pull request Jan 9, 2023
@akshay-wankhede @quekyj
Fixes: 204 - Index accesses on 1-bit signals (intel#220)
918d709
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@mkorbel1 mkorbel1 mkorbel1 approved these changes

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Generated SystemVerilog includes index access on 1-bit signals
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@akshay-wankhede @mkorbel1