Generated SystemVerilog includes index access on 1-bit signals

[mkorbel1]

Describe the bug

If a signal is defined as 1 bit in SystemVerilog:

logic x;

Then you should not access the 0'th bit of it like this:

x[0]

However, ROHD can generate this.

To Reproduce

Access the 0'th bit of a Logic and generate SystemVerilog for it.

Expected behavior

When a signal is 1 bit, treat a 0-index into it as a nop and generate accesses as just the raw signal. It's probably even better to just short-circuit this and return the signal itself immediately to save the extra work of a nop module.

Actual behavior

Generated verilog has x[0]-like behavior for 1-bit signals

Additional: Dart SDK info

No response

Additional: pubspec.yaml

No response

Additional: Context

This bug likely applies to both slice/BusSubset via constant indexing and IndexGate.

[akshay-wankhede]

I can work on this one