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[SYCL] Define SYCL_DISABLE_FALLBACK_ASSERT macro #4824
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Define SYCL_DISABLE_FALLBACK_ASSERT for FPGA Signed-off-by: Elizabeth Andrews <elizabeth.andrews@intel.com>
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LGTM
Builder.defineMacro("__ENABLE_USM_ADDR_SPACE__"); | ||
Builder.defineMacro("SYCL_DISABLE_FALLBACK_ASSERT"); |
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Unless we want a case where we enable fallback assert by default but keep it disabled for FPGA target, I assume we don't need this macro.
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Fallback assert is disabled by default due high impact issues being reported recently. Still, there's a plan to enable assert back. FPGA is an exception here as having one more kernel in device image impacts them more than GPU or CPU.
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Ok. Thank you for clarifying. @bader, I think that means we want to keep the macro? At the moment, this will have no effect but once fallback assert is enabled, the macro will keep it disables for FPGA
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Absolutely, #4694 is going to be closed. #4824 and #4780 are going to be committed. There were two types of issues:
- enabling assertions for interop kernels
- impact of assertions on FPGA
The former is fixed in [SYCL] Disable fallback assert for interop kernels #4712.
The latter is fixed with help of [SYCL] Define SYCL_DISABLE_FALLBACK_ASSERT macro #4824 and [SYCL] Disable submission of AssertInfoCopier for FPGA #4780.
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I think the second issue impacts non-FPGA devices as well. AFAIK, additional assert-specific device code is emitted for all devices even though assert is not used. Is it right? If so, what is the plan to address the overhead associated with the additional code?
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AFAIK, additional assert-specific device code is emitted for all devices even though assert is not used. Is it right?
Yes.
To overcome this impact I need to do some refactoring which is a bit stuck at limitations of sycl-post-link tool.
The limitation could be handled with employing of __sycl_kernel
attribute, though, it requires for the function to be template which isn't acceptable at the moment. Also, @AlexeySachkov can't approve the w/a in sycl-post-link I presented to him.
The overall idea of refactoring can be caught with changes of devicelib in #4987.
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Please, follow https://chris.beams.io/posts/git-commit/ and add proper PR title and description to #4987.
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Can you add test?
Tests have been already added. Sorry I missed that.
@premanandrao , a friendly ping |
There is a test in this patch for the macro. From a FE perspective, I don't think further tests are required |
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LGTM
Define SYCL_DISABLE_FALLBACK_ASSERT for FPGA
Signed-off-by: Elizabeth Andrews elizabeth.andrews@intel.com