Make Nary*IfNeeded variants keep the original order of the operands w…

…hen uniquifying.

This produces more stable output orders.

PiperOrigin-RevId: 709910975

xls/codegen/testdata/block_generator_test_LoopbackFifoInstantiation.svtxt

@@ -21,8 +21,8 @@ module running_sum(
   reg __out_data_has_been_sent_reg;
   reg __fifo_loopback_push_data_has_been_sent_reg;
   wire p2_all_active_states_valid;
-  wire __fifo_loopback_push_data_has_sent_or_is_ready;
   wire __out_data_has_sent_or_is_ready;
+  wire __fifo_loopback_push_data_has_sent_or_is_ready;
   wire p2_stage_valid;
   wire p2_all_active_inputs_valid;
   wire p2_all_active_outputs_ready;
@@ -64,11 +64,11 @@ module running_sum(
   wire __fifo_loopback_push_data_has_been_sent_reg_load_en;
 
   assign p2_all_active_states_valid = 1'h1;
-  assign __fifo_loopback_push_data_has_sent_or_is_ready = instantiation_output_1061 | __fifo_loopback_push_data_has_been_sent_reg;
   assign __out_data_has_sent_or_is_ready = out_ready | __out_data_has_been_sent_reg;
+  assign __fifo_loopback_push_data_has_sent_or_is_ready = instantiation_output_1061 | __fifo_loopback_push_data_has_been_sent_reg;
   assign p2_stage_valid = p2_all_active_states_valid & p1_valid;
   assign p2_all_active_inputs_valid = 1'h1;
-  assign p2_all_active_outputs_ready = __fifo_loopback_push_data_has_sent_or_is_ready & __out_data_has_sent_or_is_ready;
+  assign p2_all_active_outputs_ready = __out_data_has_sent_or_is_ready & __fifo_loopback_push_data_has_sent_or_is_ready;
   assign p1_all_active_states_valid = 1'h1;
   assign loopback_active_valid = ~p0_not_first_cycle | instantiation_output_1045;
   assign p2_stage_done = p2_stage_valid & p2_all_active_inputs_valid & p2_all_active_outputs_ready;

xls/codegen/testdata/block_generator_test_LoopbackFifoInstantiation.vtxt

@@ -21,8 +21,8 @@ module running_sum(
   reg __out_data_has_been_sent_reg;
   reg __fifo_loopback_push_data_has_been_sent_reg;
   wire p2_all_active_states_valid;
-  wire __fifo_loopback_push_data_has_sent_or_is_ready;
   wire __out_data_has_sent_or_is_ready;
+  wire __fifo_loopback_push_data_has_sent_or_is_ready;
   wire p2_stage_valid;
   wire p2_all_active_inputs_valid;
   wire p2_all_active_outputs_ready;
@@ -64,11 +64,11 @@ module running_sum(
   wire __fifo_loopback_push_data_has_been_sent_reg_load_en;
 
   assign p2_all_active_states_valid = 1'h1;
-  assign __fifo_loopback_push_data_has_sent_or_is_ready = instantiation_output_1061 | __fifo_loopback_push_data_has_been_sent_reg;
   assign __out_data_has_sent_or_is_ready = out_ready | __out_data_has_been_sent_reg;
+  assign __fifo_loopback_push_data_has_sent_or_is_ready = instantiation_output_1061 | __fifo_loopback_push_data_has_been_sent_reg;
   assign p2_stage_valid = p2_all_active_states_valid & p1_valid;
   assign p2_all_active_inputs_valid = 1'h1;
-  assign p2_all_active_outputs_ready = __fifo_loopback_push_data_has_sent_or_is_ready & __out_data_has_sent_or_is_ready;
+  assign p2_all_active_outputs_ready = __out_data_has_sent_or_is_ready & __fifo_loopback_push_data_has_sent_or_is_ready;
   assign p1_all_active_states_valid = 1'h1;
   assign loopback_active_valid = ~p0_not_first_cycle | instantiation_output_1045;
   assign p2_stage_done = p2_stage_valid & p2_all_active_inputs_valid & p2_all_active_outputs_ready;

xls/ir/BUILD

@@ -1317,7 +1317,6 @@ cc_library(
         "//xls/data_structures:inline_bitmap",
         "//xls/data_structures:leaf_type_tree",
         "@com_google_absl//absl/algorithm:container",
-        "@com_google_absl//absl/container:btree",
         "@com_google_absl//absl/container:flat_hash_map",
         "@com_google_absl//absl/container:flat_hash_set",
         "@com_google_absl//absl/log:check",

xls/ir/node_util.cc

@@ -26,7 +26,6 @@
 #include <vector>
 
 #include "absl/algorithm/container.h"
-#include "absl/container/btree_set.h"
 #include "absl/container/flat_hash_map.h"
 #include "absl/container/flat_hash_set.h"
 #include "absl/log/check.h"
@@ -54,6 +53,24 @@
 #include "xls/ir/value_utils.h"
 
 namespace xls {
+namespace {
+
+// Produces a vector of nodes from the given span removing duplicates. The
+// first instance of each node is kept and subsequent duplicates are dropped,
+// e.g. RemoveDuplicateNodes({a, b, a, c, a, d}) -> {a, b, c, d}.
+std::vector<Node*> RemoveDuplicateNodes(absl::Span<Node* const> values) {
+  absl::flat_hash_set<Node*> unique_values_set(values.begin(), values.end());
+  std::vector<Node*> unique_values_vector;
+  unique_values_vector.reserve(unique_values_set.size());
+  for (Node* value : values) {
+    if (auto extracted = unique_values_set.extract(value)) {
+      unique_values_vector.push_back(extracted.value());
+    }
+  }
+  return unique_values_vector;
+}
+
+}  // namespace
 
 bool IsLiteralWithRunOfSetBits(Node* node, int64_t* leading_zero_count,
                                int64_t* set_bit_count,
@@ -347,15 +364,12 @@ absl::StatusOr<Node*> NaryAndIfNeeded(FunctionBase* f,
     return f->MakeNodeWithName<Literal>(source_info, Value(UBits(1, 1)), name);
   }
 
-  absl::btree_set<Node*, Node::NodeIdLessThan> unique_operands(operands.begin(),
-                                                               operands.end());
+  std::vector<Node*> unique_operands = RemoveDuplicateNodes(operands);
   if (unique_operands.size() == 1) {
-    return operands[0];
+    return unique_operands[0];
   }
-  return f->MakeNodeWithName<NaryOp>(
-      source_info,
-      std::vector<Node*>(unique_operands.begin(), unique_operands.end()),
-      Op::kAnd, name);
+  return f->MakeNodeWithName<NaryOp>(source_info, unique_operands, Op::kAnd,
+                                     name);
 }
 
 absl::StatusOr<Node*> NaryOrIfNeeded(FunctionBase* f,
@@ -366,31 +380,27 @@ absl::StatusOr<Node*> NaryOrIfNeeded(FunctionBase* f,
     return f->MakeNodeWithName<Literal>(source_info, Value(UBits(0, 1)), name);
   }
 
-  absl::btree_set<Node*, Node::NodeIdLessThan> unique_operands(operands.begin(),
-                                                               operands.end());
+  std::vector<Node*> unique_operands = RemoveDuplicateNodes(operands);
   if (unique_operands.size() == 1) {
-    return operands[0];
+    return unique_operands[0];
   }
-  return f->MakeNodeWithName<NaryOp>(
-      source_info,
-      std::vector<Node*>(unique_operands.begin(), unique_operands.end()),
-      Op::kOr, name);
+  return f->MakeNodeWithName<NaryOp>(source_info, unique_operands, Op::kOr,
+                                     name);
 }
 
 absl::StatusOr<Node*> NaryNorIfNeeded(FunctionBase* f,
                                       absl::Span<Node* const> operands,
                                       std::string_view name,
                                       const SourceInfo& source_info) {
   XLS_RET_CHECK(!operands.empty());
-  absl::btree_set<Node*, Node::NodeIdLessThan> unique_operands(operands.begin(),
-                                                               operands.end());
+
+  std::vector<Node*> unique_operands = RemoveDuplicateNodes(operands);
   if (unique_operands.size() == 1) {
-    return f->MakeNodeWithName<UnOp>(source_info, operands[0], Op::kNot, name);
+    return f->MakeNodeWithName<UnOp>(source_info, unique_operands[0], Op::kNot,
+                                     name);
   }
-  return f->MakeNodeWithName<NaryOp>(
-      source_info,
-      std::vector<Node*>(unique_operands.begin(), unique_operands.end()),
-      Op::kNor, name);
+  return f->MakeNodeWithName<NaryOp>(source_info, unique_operands, Op::kNor,
+                                     name);
 }
 
 bool IsUnsignedCompare(Node* node) {

xls/ir/node_util_test.cc

@@ -481,8 +481,8 @@ TEST_F(NodeUtilTest, NaryNorWithMultipleInputs) {
       NaryNorIfNeeded(
           f, std::vector<Node*>{a0.node(), a3.node(), a2.node(), a1.node(),
                                 a4.node(), a1.node(), a3.node(), a1.node()}),
-      IsOkAndHolds(m::Nor(m::Param("a0"), m::Param("a1"), m::Param("a2"),
-                          m::Param("a3"), m::Param("a4"))));
+      IsOkAndHolds(m::Nor(m::Param("a0"), m::Param("a3"), m::Param("a2"),
+                          m::Param("a1"), m::Param("a4"))));
 }
 
 TEST_F(NodeUtilTest, ChannelUsers) {

xls/tools/testdata/codegen_main_test__test_add_idle_output_proc.vtxt

@@ -45,5 +45,5 @@ module neg_proc(
   assign out = __out_reg;
   assign out_vld = __out_valid_reg;
   assign in_rdy = in_load_en;
-  assign idle = ~(in_vld | __in_valid_reg | __out_valid_reg);
+  assign idle = ~(__in_valid_reg | __out_valid_reg | in_vld);
 endmodule