fix(sync): balance multi-tile prefetch event boundaries

[zhangstevenunity]

A preload followed by a multi-tile prefetch loop initialized and drained every slot event, allowing reads or overwrites before their dependencies completed and leaving unmatched waits for odd trip counts. Compute entry and exit events from each slot's first set/wait order and the loop's final rotation position, including loops with zero iterations.

Keep boundary events scoped to their owning loop and avoid duplicate enclosing-loop events. Preserve static synchronization for unproven distinct slot expressions, and use the existing PIPE_ALL fallback when a proven rotation cannot obtain enough event IDs. Update the design documentation and strengthen the existing boundary checks.

Validation:

• Full lit suite: 1,871 passed, 1 unsupported (VFSIM cost model disabled). After the final change for event exhaustion, rebuilt and reran all 89 sync/multi_tile/event tests; all passed.
• New protocol regression: 30 level2/level3 configurations and 434 total executions, checking binary-event balance and tile RAW/WAR/WAW ordering. Covers odd/even/zero trips, alternate slot expressions, nested loops, epilogues, and N=2/3/4/8/16.
• WSL CANN 8.5 Ascend910B1 simulator: the old 7-trip kernel hangs until the 60-second timeout; fixed 1/7/8-trip kernels finish with zero mismatches and zero maximum error. The final compiler emits byte-identical C++ to the simulated kernels.
• The old 8-trip kernel also passes on this local model, so the reported even-trip device race was checked through the protocol regression rather than reproduced on hardware. CANN 9.0 hardware was not tested.
• All builds used one job. Code compliance checks and git diff --check passed.

Fixes #1519.

[chatgpt-codex-connector]

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