[FIRRTL][OMIR] Add omir output file option to firtool. NFC. (llvm#2028)

This commit adds the option `--output-omir` to specify the output file for OMIR output json.
hunterzju · Oct 22, 2021 · 47bd2df · 47bd2df
1 parent b77f14b
commit 47bd2df
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diff --git a/test/firtool/firtool.fir b/test/firtool/firtool.fir
@@ -5,6 +5,7 @@
 ; RUN: firtool %s --format=fir -verilog |             FileCheck %s --check-prefix=VERILOG
 ; RUN: firtool %s --annotation-file %s.anno.json,%s.anno.1.json --mlir --parse-only | FileCheck %s --check-prefix=ANNOTATIONS
 ; RUN: firtool %s --omir-file %s.omir.anno.json --parse-only | FileCheck %s --check-prefix=OMIR
+; RUN: firtool %s --omir-file %s.omir.anno.json --output-omir meta.omir.json --verilog | FileCheck %s --check-prefix=OMIROUT
 
 circuit test_mod : %[[{"a": "a"}]]
 
@@ -29,6 +30,18 @@ circuit test_mod : %[[{"a": "a"}]]
 ; OMIR-SAME:      id = "OMID:0",
 ; OMIR-SAME:      info = #loc1}]}
 
+
+; OMIROUT-LABEL: FILE "meta.omir.json" -----
+; OMIROUT:     "info": "@[Foo.scala 32:32]",
+; OMIROUT-NEXT:     "id": "OMID:0",
+; OMIROUT-NEXT:     "fields": [
+; OMIROUT-NEXT:       {
+; OMIROUT-NEXT:         "info": "@[Foo.scala 64:64 Bar.scala 128:128]",
+; OMIROUT-NEXT:         "name": "stringVal",
+; OMIROUT-NEXT:         "value": "OMString:hello"
+; OMIROUT-NEXT:       }
+
+
   module test_mod :
     input clock : Clock
     input a: UInt<1>

diff --git a/tools/firtool/firtool.cpp b/tools/firtool/firtool.cpp
@@ -226,6 +226,10 @@ static cl::list<std::string>
                        cl::desc("Optional input object model 2.0 file"),
                        cl::CommaSeparated, cl::value_desc("filename"));
 
+static cl::opt<std::string>
+    omirOutFile("output-omir", cl::desc("file name for the output omir"),
+                cl::init(""));
+
 static cl::opt<std::string> blackBoxRootPath(
     "blackbox-path",
     cl::desc("Optional path to use as the root of black box annotations"),
@@ -396,7 +400,8 @@ processBuffer(MLIRContext &context, TimingScope &ts, llvm::SourceMgr &sourceMgr,
         replSeqMem, replSeqMemCircuit, replSeqMemFile));
 
   if (emitOMIR)
-    pm.nest<firrtl::CircuitOp>().addPass(firrtl::createEmitOMIRPass());
+    pm.nest<firrtl::CircuitOp>().addPass(
+        firrtl::createEmitOMIRPass(omirOutFile));
 
   // Lower if we are going to verilog or if lowering was specifically requested.
   if (lowerToHW || outputFormat == OutputVerilog ||