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Commits on Jul 29, 2022

• Updated Vivado gitignore

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Commits on Jul 12, 2022

• Added Verilog versions of UART components

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Commits on Jul 3, 2022

• Updated testbench template

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  0d9f67f

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• Update Modelsim gitignore

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Commits on Jun 19, 2022

• Updated tb template with clock gen module

  pConst

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• Added configurable simulation clock gen

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Commits on Jun 16, 2022

• Straight and simple realization of recursive scripts

  pConst

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  49fefc9

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• Updated testbench template project

  pConst

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  783c33e

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• Added pattern detector and tb

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Commits on Jun 6, 2022

• Added optional filtering

  pConst

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• Added fifo combiner

  pConst

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  f7c4995

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• Updated scripts

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Commits on Jun 1, 2022

• Removed obsolete files. Updated scripts

  pConst

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Commits on May 20, 2022

• Updated Vivado clean script

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Commits on May 16, 2022

• Added reference souce code dir

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• More README fixes

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  864a690

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• Fixed READMEs

  pConst

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• Added benchmark_projects dir README

  pConst

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  66733fa

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• Added reference benchmark project for Gowin IDE

  pConst

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  f6a5726

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• Added gitignore and clen script for Gowin IDE projects

  pConst

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  68ec411

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• Added Fmax test project for Gowin

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Commits on May 1, 2022

• Added Fmax test projects for Quartus and for Vivado

  pConst

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• Added Fmax computation script for Xilinx Vivado

  pConst

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• Done fifo buffer and tests

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  9ea8e5e

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• Minor style fixes

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Commits on Apr 25, 2022

• Added read ahead buffer

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Commits on Apr 24, 2022

• Done fifo initialization

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  a6aa3c3

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• Added error suppression for Modelsim script

  pConst

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Commits on Apr 23, 2022

• Added fifo initialization

  pConst

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• Added simple UART logger

  pConst

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Commits on Apr 5, 2022

• Updated mem_writer scripts and example output

  pConst

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  c6d4f60

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• Updated test projects to support dev boards

  pConst

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Commits on Mar 31, 2022

• Added RAM templates

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• Added clogb2 function

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• Changed reset mode to asynchronous for soft_latch.sv

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